Chapter1
Configuration Overview
Overview
Spartan?-6 FPGAs are configured by loading application-specific configuration data—a bitstream—into internal memory. Spartan-6 FPGAs can load themselves from an external nonvolatile memory device or they can be configured by an external smart source, such as a microprocessor, DSP processor, microcontroller, PC, or board tester. In any case, there are two general configuration datapaths. The first is the serial datapath that is used to
minimize the device pin requirements. The second datapath is the 8- or 16-bit datapath used for higher performance or access (or link) to industry-standard interfaces, ideal for external data sources like processors, or x8- or x16-parallel flash memory.
Like processors and processor peripherals, Xilinx? FPGAs can be reprogrammed, in system, on demand, an unlimited number of times.
Because Xilinx FPGA configuration data is stored in CMOS configuration latches (CCLs), it must be reconfigured after it is powered down. The bitstream is loaded each time into the device through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes:?????
JTAG configuration mode
Master Serial/SPI configuration mode (x1, x2, and x4)Slave Serial configuration mode
Master SelectMAP/BPI configuration mode (x8 and x16)Slave SelectMAP configuration mode (x8 and x16)
The configuration modes are explained in detail in Chapter2, Configuration Interface Basics.
The specific configuration mode is selected by setting the appropriate level on the mode input pins M[1:0]. The M1 and M0 mode pins should be set at a constant DC voltage level and tied directly to ground or VCCO_2. The mode pins should not be toggled during or before configuration but can be toggled after. See Chapter2, Configuration Interface Basics, for the mode pin setting options.
The terms Master and Slave refer to the direction of the configuration clock (CCLK):?
In Master configuration modes, the Spartan-6 device drives CCLK from an internaloscillator by default or optional external master clock source GCLK0/USERCCLK. Toselect the desired frequency, the BitGen -g ConfigRate option is used for theinternal oscillator. The default is 2MHz. The CCLK output frequency varies withprocess, voltage, and temperature. The data sheet FMCCKTOL specification defines thefrequency tolerance. A frequency tolerance of ±50% means that a ConfigRate settingof 10 could generate a CCLK rate of between 5MHz and 15MHz.The BitGen section
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 6:Readback and Configuration Verification
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 5:Configuration Details
FDRO Register
The FDRO is for reading configuration data or captured data from the device. Loading the command register with the RCFG command, and then addressing the FDRO with a read command perform a readback.
MASK Register
MASK register performs writes to the CTL register. A 1 in bit N of the mask allows that bit position to be written in the CTL register. The default value of the mask is 0.
EYE_MASK Register
The EYE_MASK register stores the mask for the SCP pins for the Multi-Pin Wake-Up feature. It is 16bits, with the lower 8 representing the mask. The upper 8 bits are reserved. The lower 8 bits are set from the -g wakeup_mask BitGen option.
LOUT Register
The Legacy Output Register (LOUT) is used for daisy-chaining the configuration bit
stream to other Xilinx devices. Data written to the LOUT is serialized and appears on the DOUT pin.
CBC_REG Register
This register is used by the bitstream compression option to hold the Initial Vector (IV) for AES decryption.
IDCODE Register
Any writes to the FDRI register must be preceded by a write to this register. The provided IDCODE must match the device’s IDCODE. See Configuration Sequence, page82.A read of this register returns the device IDCODE.
CSBO Register
The CSBO register is designed to assert the CSB_O signal and then ignore any incoming data for a specified word count. It works much the same way as the LOUT register except that it only outputs a Low on CSB_O and no data is passed through. Like the LOUT register, multiple calls can be nested for different devices in support of daisy-chaining.
Command Register (CMD)
The Command Register is used to instruct the configuration control logic to strobe global signals and perform other configuration functions. The command present in the CMD register is executed each time the FAR is loaded with a new value. Table5-33 lists the Command Register commands and codes.Table 5-33:CommandNULLWCFG
Command Register Codes
Code0000000001
Null Command
Writes Configuration Data: Used prior to writing configuration data to the FDRI.
Description
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Configuration Packets
Table 5-33:CommandMFWLFRM
Command Register Codes (Cont’d)
Code0001000011
Description
Multiple Frame Write: Used to perform a write of a single frame data to multiple frame addresses.
Last Frame: Deasserts the GHIGH_B signal, activating all
interconnects. The GHIGH_B signal is asserted with the AGHIGH command.
Reads Configuration Data: Used prior to reading configuration data from the FDRO.
Begins the Startup Sequence: Initiates the startup sequence. The startup sequence begins after a successful CRC check and a DESYNC command are performed.Resets CRC: Resets the CRC register.
Asserts the GHIGH_B signal: Places all interconnect in a high-Z state to prevent contention when writing new configuration data. This command is only used in shutdown reconfiguration. Interconnect is reactivated with the LFRM command.Pulses the GRESTORE signal: Sets/resets (depending on user configuration) IOB and CLB flip-flops.
Begins the shutdown sequence: Initiates the shutdown sequence, disabling the device when finished. Shutdown activates on the next successful CRC check or RCRC instruction (typically, an RCRC instruction).
Resets the DALIGN Signal: Used at the end of configuration to desynchronize the device. After desynchronization, all values on the configuration data pins are ignored.
Generates reboot_rst to reconfigure from the address specified in the general register.
RCFGSTART
0010000101
RCRCAGHIGH
0011101000
GRESTORESHUTDOWN
0101001011
DESYNC01101
IPROG01110
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 7:Reconfiguration and MultiBoot
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
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