High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 39. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Table 39. HSE oscillator characteristics
SymbolfOSC_INRF
Parameter
Oscillator frequencyFeedback resistor
Conditions(1)
--During startup(3)VDD = 3.3 V, Rm = 30 ?, CL = 10 pF@8 MHzVDD = 3.3 V, Rm = 45 ?, CL = 10 pF@8 MHz
IDD
HSE current consumption
VDD = 3.3 V, Rm = 30 ?, CL = 5 pF@32 MHzVDD = 3.3 V, Rm = 30 ?,
CL = 10 pF@32 MHzVDD = 3.3 V, Rm = 30 ?, CL = 20 pF@32 MHz
gm
Oscillator transconductance
Startup VDD is stabilized
tSU(HSE)(4)Startup time
2.Guaranteed by design, not tested in production.
3.This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4.tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantlywith the crystal manufacturer
Min(2)4---
Typ8200-0.4
Max(2)32-8.5-
UnitMHzk?
-0.5-mA
-0.8-
-1-
-10-
1.5-2
---mA/Vms
1.Resonator characteristics given by the crystal/ceramic resonator manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.
DS9826 Rev 6
STM32F072x8 STM32F072xBElectrical characteristics
Figure 17. Typical application with an 8 MHz crystalResonator with integrated capacitorsCL1OSC_INfHSERFBias controlled gain8 MHz resonatorREXT(1)OSC_OUTCL2MS19876V11.REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 40. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(1)low drive capability
IDD
LSE current consumption
medium-low drive capabilitymedium-high drive capability
high drive capabilitylow drive capability
gm
Oscillator transconductance
medium-low drive capabilitymedium-high drive capability
high drive capability
tSU(LSE)(3)
Startup time
VDDIOx is stabilized
Min(2)----581525-Typ0.5-------2
Max(2)Unit0.911.31.6-----sμA/VμA
1.Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.2.Guaranteed by design, not tested in production.3.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation isreached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
DS9826 Rev 6
Electrical characteristics
Software recommendations
STM32F072x8 STM32F072xB
The software flowchart must include the management of runaway conditions such as:???
Corrupted program counterUnexpected reset
Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.
Table 49. EMI characteristics
SymbolParameter
Conditions
Monitoredfrequency band0.1 to 30 MHz
Max vs. [fHSE/fHCLK]
8/48 MHz
-227174
-dBμVUnit
SEMI
VDD = 3.6 V, TA = 25 °C,
30 to 130 MHzLQFP100 package
Peak level
compliant with 130 MHz to 1 GHzIEC 61967-2
EMI Level
6.3.12 Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the standards stated in the following table.
DS9826 Rev 6
STM32F072x8 STM32F072xB
Table 50. ESD absolute maximum ratings
SymbolVESD(HBM)VESD(CDM)
Ratings
Conditions
Electrical characteristics
Packages
All
Class2C1C2a
Maximum
Unit
value(1)2000250500
VV
Electrostatic discharge voltage TA = +25 °C, conforming to (human body model)ANSI/ESDA/JEDEC JS-001
Electrostatic discharge voltage TA = +25 °C, conforming to WLCSP49(charge device model)ANSI/ESDA/JEDEC JS-002All others
1.Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up performance: ??
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 51. Electrical sensitivities
SymbolLU
ParameterStatic latch-up class
Conditions
TA = +105 °C conforming to JESD78A
ClassII level A
6.3.13 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 μA/+0 μA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).
The characterization results are given in Table 52.
Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.
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Electrical characteristicsSTM32F072x8 STM32F072xB
Table 52. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Negative Positive injectioninjection
Injected current on BOOT0 and PF1 pinsInjected current on PC0 pin
IINJ
Injected current on PA11 and PA12 pins with induced leakage current on adjacent pins less than -1 mAInjected current on all other FT and FTf pinsInjected current on all other TTa, TC and RST pins
–0–0–5–5–5
NA +5NANA+5
mAUnit
DS9826 Rev 6
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