EDA技术试验指导书new - Quartus(1)

实验二简单组合电路的设计

一位全加器的VHDL描述：

半加器的VHDL描述：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS

PORT (a, b: IN STD_LOGIC; co, so: OUT STD_LOGIC); END ENTITY h_adder;

ARCHITECTURE fh1 OF h_adder IS BEGIN

so <=NOT (a XOR (NOT b));co<=a AND b;

END ARCHITECTURE fh1; 或门的VHDL描述： LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a IS

PORT (a ,b: IN STD_LOGIC; c: out STD_LOGIC); END ENTITY or2a;

ARCHITECTURE one OF or2a IS BEGIN

c <= a OR b;

END ARCHITECTURE one; 一位全加器的VHDL描述： LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder IS

PORT ( ain, bin, cin :IN STD_LOGIC;

cout,sum:out STD_LOGIC); END ENTITY f_adder;

ARCHITECTURE fd2 OF f_adder IS COMPONENT h_adder

PORT(a,b:IN STD_LOGIC; co,so:OUT STD_LOGIC); END COMPONENT; COMPONENT or2a

PORT(a,b:IN STD_LOGIC; c:OUT STD_LOGIC); END COMPONENT:

SIGNAL d,e,f:STD_LOGIC;

BEGIN

u1:h_adder PORT MAP(a=>ain,b=>bin,co=>d,so=>e);

u2:h_adder PORT MAP(a=>e,b=>cin,co=>f,so=>sum); u3: or2a PORT MAP(a=>d,b=>f,c=>cout); END ARCHITECTURE fd2;

二选一数据选择器的VHDL描述： LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21a IS

PORT (a,b:IN BIT;s:IN BIT;y:OUT BIT);

END ENTITY mux21a;

ARCHITECTURE one OF mux21a IS BEGIN

y<=a WHEN s='0' ELSE b; END ARCHITECTURE one;

四选一数据选择器的VHDL描述： library ieee;

use ieee.std_logic_1164.all; entity mux41a is

port (d0,d1,d2,d3,a0,a1:in std_logic;

yout:out std_logic); end entity mux41a;

architecture fd1 of mux41a is component mux21a

port (a,b,s:in std_logic; y:out std_logic); end component;

signal e,f:std_logic; begin u1:mux21a port map(a=>d0,b=>d2,s=>a1,y=>e);

u2:mux21a port map(a=>d1,b=>d3,s=>a1,y=>f); u3:mux21a port map(a=>e,b=>f,s=>a0,y=>yout); end architecture fd1;

实验三简单时序电路的设计 D触发器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY D1 IS

PORT(CLK,D :IN STD_LOGIC; Q :OUT STD_LOGIC); END;

ARCHITECTURE bhv OF D1 IS SIGNAL Q1 :STD_LOGIC; BEGIN

PROCESS(CLK,Q1) BEGIN

IF CLK'EVENT AND CLK ='1' THEN Q1<=D; END IF; END PROCESS; Q<=Q1; END bhv;

异步清零D触发器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY D2 IS

PORT(CLK,D,rst :IN STD_LOGIC; Q :OUT STD_LOGIC); END;

ARCHITECTURE bhv OF D2 IS SIGNAL Q1 :STD_LOGIC; BEGIN

PROCESS(CLK,rst,Q1) BEGIN

IF rst='1' then Q1<='0'; ELSIF CLK'EVENT AND CLK ='1' THEN Q1<=D; END IF; END PROCESS; Q<=Q1; END bhv;

同步清零D触发器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY D3 IS

PORT(CLK,D,rst :IN STD_LOGIC; Q :OUT STD_LOGIC); END;

ARCHITECTURE bhv OF D3 IS SIGNAL Q1 :STD_LOGIC; BEGIN

PROCESS(CLK,rst,Q1) BEGIN

IF CLK'EVENT AND CLK ='1' THEN Q1<=D;

IF rst='1' then Q1<='0'; END IF; END IF; END PROCESS; Q<=Q1; END bhv;

锁存器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY D4 IS

PORT(E,D :IN STD_LOGIC; Q :OUT STD_LOGIC); END;

ARCHITECTURE bhv OF D4 IS SIGNAL Q1 :STD_LOGIC; BEGIN

PROCESS(E,Q1) BEGIN

IF E='1'

THEN Q1<=D; END IF; END PROCESS; Q<=Q1; END bhv;

实验四 异步清零和同步时钟使能的4位加法计数器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE

IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT4 IS PORT (RST,CLK,ENA:IN STD_LOGIC;

COUT: OUT STD_LOGIC; OUTY :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END CNT4;

ARCHITECTURE behv OF CNT4 IS BEGIN

PROCESS (RST,ENA,CLK) VARIABLE

CQI :STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

IF RST='1' THEN CQI :=(OTHERS =>'0');

ELSIF CLK'EVENT AND CLK='1' THEN

IF ENA ='1' THEN

IF CQI < 15 THEN CQI:=CQI+1; ELSE CQI :=(OTHERS =>'0'); END IF; END IF; END IF;

IF CQI =15 THEN COUT<='1'; ELSE COUT <='0'; END IF;

OUTY <=CQI; END PROCESS; END behv;

实验六 数控分频器的设计

ENTITY DVF IS

PORT(CLK:IN STD_LOGIC; D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

FOUT:OUT STD_LOGIC); END;

ARCHITECTURE ONE OF DVF IS SIGNAL FULL:STD_LOGIC; BEGIN

P_REG:PROCESS(CLK)

VARIABLE CNT8:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

IF CLK'EVENT AND CLK='1' THEN IF CNT8=\ CNT8:=D; FULL<='1';

ELSE CNT8:=CNT8+1; FULL<='0'; END IF; END IF;

END PROCESS P_REG; P_DVF:PROCESS(FULL)

VARIABLE CNT2:STD_LOGIC; BEGIN

IF FULL'EVENT AND FULL='1' THEN CNT2:=NOT CNT2;

IF CNT2='1' THEN FOUT<='1';ELSE FOUT<='0'; END IF; END IF;

END PROCESS P_DVF; END;

实验五

7段数码管显示译码电路VHDL描述

library ieee;

use ieee.std_logic_1164.all; entity decl7s is

port(a:in std_logic_vector(3 downto 0);

led7s:out std_logic_vector(6 downto 0)); end;

architecture one of decl7s is begin

process(a) begin

case a is

when\when\when\when\when\when\when\when\when\when\when\when\when\when\when\when\when others=>null; end case; end process; end;

扫描码的VHDL的描述：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SCAN_LED IS PORT(

CLK :IN STD_LOGIC; W:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); D:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END SCAN_LED;

ARCHITECTURE one OF SCAN_LED IS SIGNAL INPUT :STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN

P1:PROCESS(CLK) BEGIN

IF CLK'EVENT AND CLK='1' THEN INPUT<=INPUT+1; END IF;

END PROCESS P1 ; W<=INPUT;

P2:PROCESS(INPUT) BEGIN

CASE INPUT IS

WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS => NULL; END CASE;

END PROCESS P2; END one;

实验七 4位十进制频率计的