MSP430G2553学习笔记

注意：在MSP430G2553上电复位后，默认RSEL=7，DCO=3，通过数据手册查得DCO频率大概在0.8~1.5MHz之间。

BCSCTL1-基本时钟控制寄存器1

XT2OFF

不用管，因为MSP430G2553内部没有XT2提供的HF时钟 XTS

不用管，默认复位后的0值即可 DIVAx

设置ACLK的分频数 00 01 10 11 RSELx

DCO频率选择控制2

/1 /2 /4 /8

BCSCTL2-基本时钟控制寄存器2

SELMx

MCLK的选择控制位 00 01 10 11 DIVMx

设置MCLK的分频数 00 01 10 11 SELS

SMCLK的选择控制位 0 1 DIVSx

设置SMCLK的分频数 00 01 10 11 DCOR

DCO直流发生电阻选择，此位一般设0

0 1

内部电阻 外部电阻 /1 /2 /4 /8

DCOCLK

LFXT1CLK或者VLOCLK /1 /2 /4 /8 DCOCLK DCOCLK

LFXT1CLK或者VLOCLK LFXT1CLK或者VLOCLK

BCSCTL3-基本时钟控制寄存器3

XT2Sx

不用管

LFXT1Sx

00 01 10 11 XCAPx

LFXT1晶振谐振电容选择

00 01 10 11

1pF 6pF 10pF 12.5pF

LFXT1选为32.768KHz晶振 保留 VLOCLK 外部数字时钟源

msp430g2553.h中基本时钟系统的内容

/************************************************************ * Basic Clock Module

************************************************************/

#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */

SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */ SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */ SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */ SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */

#define MOD0 (0x01) /* Modulation Bit 0 */ #define MOD1 (0x02) /* Modulation Bit 1 */ #define MOD2 (0x04) /* Modulation Bit 2 */ #define MOD3 (0x08) /* Modulation Bit 3 */ #define MOD4 (0x10) /* Modulation Bit 4 */ #define DCO0 (0x20) /* DCO Select Bit 0 */ #define DCO1 (0x40) /* DCO Select Bit 1 */ #define DCO2 (0x80) /* DCO Select Bit 2 */

#define RSEL0 (0x01) /* Range Select Bit 0 */ #define RSEL1 (0x02) /* Range Select Bit 1 */ #define RSEL2 (0x04) /* Range Select Bit 2 */

#define RSEL3 (0x08) /* Range Select Bit 3 */ #define DIVA0 (0x10) /* ACLK Divider 0 */ #define DIVA1 (0x20) /* ACLK Divider 1 */

#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ #define XT2OFF (0x80) /* Enable XT2CLK */

#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */ #define DIVA_1 (0x10) /* ACLK Divider 1: /2 */ #define DIVA_2 (0x20) /* ACLK Divider 2: /4 */ #define DIVA_3 (0x30) /* ACLK Divider 3: /8 */

#define DIVS0 (0x02) #define DIVS1 (0x04) #define SELS (0x08) 1:XT2CLK/LFXTCLK */#define DIVM0 (0x10) #define DIVM1 (0x20) #define SELM0 (0x40) #define SELM1 (0x80)

#define DIVS_0 (0x00) #define DIVS_1 (0x02) #define DIVS_2 (0x04) #define DIVS_3 (0x06)

#define DIVM_0 (0x00) #define DIVM_1 (0x10) #define DIVM_2 (0x20) #define DIVM_3 (0x30)

#define SELM_0 (0x00) #define SELM_1 (0x40) #define SELM_2 (0x80) */

#define SELM_3 (0xC0)

#define LFXT1OF (0x01) Flag */

#define XT2OF (0x02) */

#define XCAP0 (0x04) #define XCAP1 (0x08) #define LFXT1S0 (0x10) #define LFXT1S1 (0x20) #define XT2S0 (0x40) #define XT2S1 (0x80)

/* SMCLK Divider 0 */ /* SMCLK Divider 1 */

/* SMCLK Source Select 0:DCOCLK / /* MCLK Divider 0 */ /* MCLK Divider 1 */ /* MCLK Source Select 0 */ /* MCLK Source Select 1 */ /* SMCLK Divider 0: /1 */ /* SMCLK Divider 1: /2 */ /* SMCLK Divider 2: /4 */ /* SMCLK Divider 3: /8 */ /* MCLK Divider 0: /1 */ /* MCLK Divider 1: /2 */ /* MCLK Divider 2: /4 */ /* MCLK Divider 3: /8 */ /* MCLK Source Select 0: DCOCLK */ /* MCLK Source Select 1: DCOCLK */ /* MCLK Source Select 2: XT2CLK/LFXTCLK /* MCLK Source Select 3: LFXTCLK */ /* Low/high Frequency Oscillator Fault /* High frequency oscillator 2 fault flag /* XIN/XOUT Cap 0 */ /* XIN/XOUT Cap 1 */

/* Mode 0 for LFXT1 (XTS = 0) */ /* Mode 1 for LFXT1 (XTS = 0) */ /* Mode 0 for XT2 */ /* Mode 1 for XT2 */