DS099 June 27, 2013Product Specification
Module 1:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013??????
IntroductionFeatures
Architectural OverviewArray Sizes and ResourcesUser I/O ChartOrdering Information
Module 4: Pinout Descriptions
DS099 (v3.1) June 27, 2013???
Pin Descriptions?
Pin Behavior During ConfigurationPackage OverviewPinout Tables?
Footprints
Module 2: Functional Description
DS099 (v3.1) June 27, 2013?
Input/Output Blocks (IOBs)?????
IOB Overview
SelectIO? Interface I/O Standards
Configurable Logic Blocks (CLBs)Block RAMDedicated Multipliers
???
Digital Clock Manager (DCM)Clock NetworkConfiguration
Module 3:
DC and Switching Characteristics
DS099 (v3.1) June 27, 2013?
DC Electrical Characteristics?????
????
Absolute Maximum RatingsSupply Voltage SpecificationsRecommended Operating ConditionsDC CharacteristicsI/O Timing
Internal Logic TimingDCM Timing
Configuration and JTAG Timing
Switching Characteristics
DS099 June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
Table 71:Dual-Purpose Pins Used in Master or Slave Serial Mode
Pin NameDIN
DirectionInput
Description
Serial Data Input:
During the Master or Slave Serial configuration modes, DIN is the serial configuration data input, and all data is synchronized to the rising CCLK edge. After configuration, this pin is available as a user I/O. This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.Serial Data Output:
In a multi-FPGA design where all the FPGAs use serial mode, connect the DOUT output of one FPGA—in either Master or Slave Serial mode—to the DIN input of the next FPGA—in Slave Serial mode—so that configuration data passes from one to the next, in daisy-chain fashion. This “daisy chain” permits sequential configuration of multiple FPGAs.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.Initializing Configuration Memory/Configuration Error:
Just after power is applied, the FPGA produces a Low-to-High transition on this pin indicating that initialization (i.e., clearing) of the configuration memory has finished. Before entering the User mode, this pin functions as an open-drain output, which requires a pull-up resistor in order to produce a High logic level. In a multi-FPGA design, tie (wire AND) the INIT_B pins from all FPGAs together so that the common node transitions High only after all of the FPGAs have been successfully initialized.
Externally holding this pin Low beyond the initialization phase delays the start of configuration. This action stalls the FPGA at the configuration step just before the mode select pins are sampled.During configuration, the FPGA indicates the occurrence of a data (i.e., CRC) error by asserting INIT_B Low.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
DOUTOutput
INIT_B
Bidirectional (open-drain)
X-Ref Target - Figure 41I/O Bank 4 (VCCO_4)I/O Bank 5 (VCCO_5)
D31
D41
Low NibbleD5D61
0
D70(LSB)
Configuration Data Byte
0xFC =
D01(MSB)
High Nibble
D1D21
1
Figure 41:Configuration Data Byte Mapping to D0-D7 Bits
Parallel Configuration Modes (SelectMAP)
This section describes the dual-purpose configuration pins used during the Master and Slave Parallel configuration modes,
sometimes also called the SelectMAP modes. In both Master and Slave Parallel configuration modes, D0-D7 form the byte-wide configuration data input. See Table75 for Mode Select pin settings required for Parallel modes.
As shown in Figure41, D0 is the most-significant bit while D7 is the least-significant bit. Bits D0-D3 form the high nibble of the byte and bits D4-D7 form the low nibble.
In the Parallel configuration modes, both the VCCO_4 and VCCO_5 voltage supplies are required and must both equal the voltage of the attached configuration device, typically either 2.5V or 3.3V.
Assert Low both the chip-select pin, CS_B, and the read/write control pin, RDWR_B, to write the configuration data byte presented on the D0-D7 pins to the FPGA on a rising-edge of the configuration clock, CCLK. The order of CS_B and RDWR_B does not matter, although RDWR_B must be asserted throughout the configuration process. If RDWR_B is de-asserted during configuration, the FPGA aborts the configuration operation.
After configuration, these pins are available as general-purpose user I/O. However, the SelectMAP configuration interface is optionally available for debugging and dynamic reconfiguration. To use these SelectMAP pins after configuration, set the Persist bitstream generation option.
The Readback debugging option, for example, requires the Persist bitstream generation option. During Readback mode, assert CS_B Low, along with RDWR_B High, to read a configuration data byte from the FPGA to the D0-D7 bus on a rising CCLK edge. During Readback mode, D0-D7 are output pins.
In all the cases, the configuration data and control signals are synchronized to the rising edge of the CCLK clock signal.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
HSWAP_EN: Disable Pull-up Resistors During Configuration
As shown in Table76, a Low on this asynchronous pin enables pull-up resistors on all user I/Os not actively involved in the configuration process, although only until device configuration completes. A High disables the pull-up resistors during configuration, which is the desired state for some applications.
The dedicated configuration CONFIG pins (CCLK, DONE, PROG_B, HSWAP_EN, M2, M1, M0), the JTAG pins (TDI, TMS, TCK, TDO) and the INIT_B always have active pull-up resistors during configuration, regardless of the value on HSWAP_EN.
After configuration, HSWAP_EN becomes a \are disabled. If a user I/O in the application requires a pull-up resistor after configuration, place a PULLUP primitive on the associated I/O pin or, for some pins, set the associated bitstream generator option.Table 76:HSWAP_EN Encoding
HSWAP_ENDuring Configuration
01
Enable pull-up resistors on all pins not actively involved in the configuration process. Pull-ups are only active until configuration completes. See Table79.No pull-up resistors during configuration.
Function
After Configuration, User Mode
X
Notes:
1.
X=don’t care, either 0 or 1.
This pin has no function except during device configuration.
The Bitstream generator option HswapenPin determines whether a pull-up resistor to VCCAUX, a pull-down resistor, or no resistor is present on HSWAP_EN after configuration.
JTAG: Dedicated JTAG Port Pins
Table 77:JTAG Pin Descriptions
Pin NameTCK
DirectionInput
DescriptionBitstream Generation Option
Test Clock: The TCK clock signal synchronizes all boundary The BitGen option TckPin determines scan operations on its rising edge.whether a pull-up resistor, pull-down
resistor or no resistor is present.Test Data Input: TDI is the serial data input for all JTAG instruction and data registers. This input is sampled on the rising edge of TCK.
Test Mode Select: The TMS input controls the sequence of states through which the JTAG TAP state machine passes. This input is sampled on the rising edge of TCK.
The BitGen option TdiPin determines whether a pull-up resistor, pull-down resistor or no resistor is present.The BitGen option TmsPin determines whether a pull-up resistor, pull-down resistor or no resistor is present.
TDIInput
TMSInput
TDOOutput
Test Data Output: The TDO pin is the data output for all JTAG The BitGen option TdoPin determines instruction and data registers. This output is sampled on the whether a pull-up resistor, pull-down rising edge of TCK. The TDO output is an active totem-pole resistor or no resistor is present.driver and is not like the open-collector TDO output on Virtex?-II Pro FPGAs.
These pins are dedicated connections to the four-wire IEEE 1532/IEEE 1149.1 JTAG port, shown in Figure43 and
described in Table77. The JTAG port is used for boundary-scan testing, device configuration, application debugging, and possibly an additional serial port for the application. These pins are dedicated and are not available as user-I/O pins. Every package has four dedicated JTAG pins and these pins are powered by the +2.5V VCCAUX supply.For additional information on JTAG configuration, see Boundary-Scan (JTAG) Mode, page50.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
All VCCAUX inputs must be connected together and to the +2.5V voltage supply. Furthermore, there must be sufficient supply decoupling to guarantee problem-free operation, as described in XAPP623.
Because VCCAUX connects to the DCMs and the DCMs are sensitive to voltage changes, be sure that the VCCAUX supply and the ground return paths are designed for low noise and low voltage drop, especially that caused by a large number of simultaneous switching I/Os.
GND Type: Ground
All GND pins must be connected and have a low resistance path back to the various VCCO, VCCINT, and VCCAUX supplies.
Pin Behavior During Configuration
Table79 shows how various pins behave during the FPGA configuration process. The actual behavior depends on the values applied to the M2, M1, and M0 mode select pins and the HSWAP_EN pin. The mode select pins determine which of the DUAL type pins are active during configuration. In JTAG configuration mode, none of the DUAL-type pins are used for configuration and all behave as user-I/O pins.
All DUAL-type pins not actively used during configuration and all I/O-type, DCI-type, VREF-type, GCLK-type pins are high impedance (floating, three-stated, Hi-Z) during the configuration process. These pins are indicated in Table79 as shaded table entries or cells. These pins have a pull-up resistor to their associated VCCO if the HSWAP_EN pin is Low. When HSWAP_EN is High, these pull-up resistors are disabled during configuration.
Some pins always have an active pull-up resistor during configuration, regardless of the value applied to the HSWAP_EN pin. After configuration, these pull-up resistors are controlled by Bitstream Options.???
All the dedicated CONFIG-type configuration pins (CCLK, PROG_B, DONE, M2, M1, M0, and HSWAP_EN) have apull-up resistor to VCCAUX.
All JTAG-type pins (TCK, TDI, TMS, TDO) have a pull-up resistor to VCCAUX.
The INIT_B DUAL-purpose pin has a pull-up resistor to VCCO_4 or VCCO_BOTTOM, depending on package style.
After configuration completes, some pins have optional behavior controlled by the configuration bitstream loaded into the part. For example, via the bitstream, all unused I/O pins can be collectively configured as input pins with either a pull-up resistor, a pull-down resistor, or be left in a high-impedance state.Table 79:Pin Behavior After Power-Up, During Configuration
Configuration Mode Settings
Pin Name
Serial Modes
Master <0:0:0>
I/O: General-purpose I/O pinsIOIO_Lxxy_#
UnusedPinUnusedPin
SelectMap Parallel ModesMaster <0:1:1>
Slave <1:1:0>
Slave <1:1:1>
JTAG Mode <1:0:1>
Bitstream Configuration
Option
DUAL: Dual-purpose configuration pinsIO_Lxxy_#/DIN/D0IO_Lxxy_#/D1IO_Lxxy_#/D2IO_Lxxy_#/D3IO_Lxxy_#/D4
DIN (I)
DIN (I)
D0 (I/O)D1 (I/O)D2 (I/O)D3 (I/O)D4 (I/O)
D0 (I/O)D1 (I/O)D2 (I/O)D3 (I/O)D4 (I/O)
Persist UnusedPinPersist UnusedPinPersist UnusedPinPersist UnusedPinPersist UnusedPin
DS099 (v3.1) June 27, 2013Product Specification
相关推荐：
loading