EDA数字时钟实验

3.2晶体振荡器

晶体振荡电路是构成数字式时钟的核心，它保证了时钟走时准确及稳定。晶体振荡器它的作用是产生时间标准信号。数字钟的精度主要取决于时间标准信号的频率及其稳定度。因此，一般采用石英晶体振荡器经过分频得到这一信号。

3.3分频器电路

分频器电路将20MHZ的高频方波信号经20M次分频后得到1Hz的方波信号供秒计数器进行计数。分频器实际上也就是计数器。

3.4 部分程序实现 思路一实现：

（1）具有调整功能的24、59进制程序

LIBRARY IEEE ;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cnt24 IS PORT( CLK1,RES,EN,KONGZHI,CLK2: IN STD_LOGIC; COUNT: OUT STD_LOGIC_VECTOR(4 DOWNTO 0); CQ : OUT STD_LOGIC); END;

ARCHITECTURE behav OF cnt24 IS SIGNAL CLK : STD_LOGIC; BEGIN PROCESS(CLK1,EN,KONGZHI,RES) VARIABLE CQI:STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN CASE KONGZHI IS WHEN '0'=> CLK <=CLK1; WHEN '1'=> CLK <=CLK2; WHEN OTHERS =>CLK<='0'; END CASE; IF RES='1' THEN CQI:=\ ELSIF CLK'EVENT AND CLK='1' THEN

IF EN='1' THEN

IF CQI<24 THEN CQI:=CQI+1; ELSE CQI:=(OTHERS=>'0'); END IF; END IF; END IF; IF CQI=24 THEN CQ<='1'; ELSE CQ<='0'; END IF; COUNT<=CQI; END PROCESS; END behav;

（2）具有清零 暂停、复位功能的59进制程序

LIBRARY IEEE ;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cnt59m IS

PORT( CLK,STOP,RES,EN: IN STD_LOGIC; COUNT: OUT STD_LOGIC_VECTOR(5 DOWNTO 0); CQ : OUT STD_LOGIC); END;

ARCHITECTURE behav OF cnt59m IS SIGNAL CK : STD_LOGIC; BEGIN

PROCESS(CLK,EN,STOP,RES)

VARIABLE CQI:STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN CK<=(CLK OR STOP); IF RES='1' THEN CQI:=\ ELSIF CK'EVENT AND CK='1' THEN IF EN='1' THEN

IF CQI<59 THEN CQI:=CQI+1; ELSE CQI:=(OTHERS=>'0'); END IF; END IF; END IF;

IF CQI=59 THEN CQ<='1'; ELSE CQ<='0'; END IF;

COUNT<=CQI; END PROCESS;

END behav;

（3）转码功能程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY zhuanma IS

PORT(SHURU: IN INTEGER RANGE 0 TO 59;

GE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SHI : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END;

ARCHITECTURE bahave OF zhuanma IS BEGIN

PROCESS(SHURU) BEGIN CASE SHURU IS WHEN 0|10|20|30|40|50 => GE <=\ WHEN 1|11|21|31|41|51 => GE <=\ WHEN 2|12|22|32|42|52 => GE <=\ WHEN 3|13|23|33|43|53 => GE <=\ WHEN 4|14|24|34|44|54 => GE <=\ WHEN 5|15|25|35|45|55 => GE <=\ WHEN 6|16|26|36|46|56 => GE <=\ WHEN 7|17|27|37|47|57 => GE <=\ WHEN 8|18|28|38|48|58 => GE <=\ WHEN 9|19|29|39|49|59 => GE <=\ WHEN OTHERS => GE <=\ END CASE; CASE SHURU IS WHEN 0|1|2|3|4|5|6|7|8|9 => SHI <=\ WHEN 10|11|12|13|14|15|16|17|18|19 => SHI <=\ WHEN 20|21|22|23|24|25|26|27|28|29 => SHI <=\ WHEN 30|31|32|33|34|35|36|37|38|39 => SHI <=\ WHEN 40|41|42|43|44|45|46|47|48|49 => SHI <=\ WHEN 50|51|52|53|54|55|56|57|58|59 => SHI <=\ WHEN OTHERS => SHI <=\ END CASE; END PROCESS; END bahave;

（4）动态扫描程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY dtsm IS PORT(CLK : IN STD_LOGIC; SR1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); SR2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); SR3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); SR4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); SR5 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); SR6 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); WEI : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); DUAN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END;

ARCHITECTURE behave OF dtsm IS SIGNAL cnt6 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL A :STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN P1 : PROCESS(cnt6) BEGIN CASE cnt6 IS WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS => NULL; END CASE; END PROCESS P1; P2 : PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN IF cnt6<6 THEN cnt6<=cnt6+1; ELSE cnt6<=(OTHERS=>'0'); --IF cnt4 =\ --cnt4<=\ --ELSE cnt4<=cnt4+1; END IF; END IF; END PROCESS P2; P3: PROCESS(A)