数字钟verilog

多功能数字钟verilog HDL设计

output [5:0] disp_select; output [6:0] disp_data; output[3:0] Data;

reg [5:0] disp_select; reg [6:0] disp_data; reg [3:0] Data;

always @(Time_EN, TimeSet_EN,Stopwatch_EN,time_disp_select, Alarmclock_EN,alarmclock_disp_select,disp_select, hour1,hour0,minute1,minute0,second1,second0)

begin //时钟，秒表显示

if((Time_EN || TimeSet_EN || Stopwatch_EN) == 1'b1) begin

disp_select <= time_disp_select; case(time_disp_select)

6'b100000: Data <= hour1; 6'b010000: Data <= hour0; 6'b001000: Data <= minute1; 6'b000100: Data <= minute0; 6'b000010: Data <= second1; 6'b000001: Data <= second0; default: Data <= 4'b0; endcase end

else if(Alarmclock_EN == 1'b1) //闹钟设置显示 begin

disp_select <= alarmclock_disp_select; case(alarmclock_disp_select) 6'b100000: Data <= hour1; 6'b010000: Data <= hour0; 6'b001000: Data <= minute1; 6'b000100: Data <= minute0; default: Data <= 4'b0; endcase end

case(Data) //显示数据译码

4'b0000: disp_data <= 7'b1111110; 4'b0001: disp_data <= 7'b0110000; 4'b0010: disp_data <= 7'b1101101; 4'b0011: disp_data <= 7'b1111001; 4'b0100: disp_data <= 7'b0110011; 4'b0101: disp_data <= 7'b1011011; 4'b0110: disp_data <= 7'b1011111; 4'b0111: disp_data <= 7'b1110000; 4'b1000: disp_data <= 7'b1111111;

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多功能数字钟verilog HDL设计

4'b1001: disp_data <= 7'b1111011; default: disp_data <= 7'b0; endcase end

endmodule

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