基于Verilog的数字频率计的设计包含代码及仿真

begin count2<=0;clk_10hz<=~clk_10hz;end else count2<=count2+1; if(count3==240000)

begin count3<=0;clk_100hz<=~clk_100hz;end else count3<=count3+1; if(count4==24000)

begin count4<=0;clk_1khz<=~clk_1khz;end else count4<=count4+1; end end endmodule

仿真图

仿真模块

，门控电路和清零，锁存，阀门信号产生程序 二

module chose(rest,clk_10hz,clk_100hzhz,clk_1khz,key1,key10,key100, gate_out1,ff,clk_latch,clk_clear);

input rest ,clk_10hz,clk_100hz,clk_1khz,key1,key10,key100; output gate_out1,clk_latch,clk_clear; output reg [2:1] ff;

reg gate_out1,clk_latch,clk_clear,gate; reg [4:1]count;

initial begin gate_out1=0;ff=0;clk_latch=0;clk_clear=0;gate=0;count=0;end always@( posedge clk_1khz) begin

if(!rest) begin gate_out1<=0; ff<=2'b00;end else begin

if(key1==1&&key10==0&&key100==0) begin gate<=clk_10hz; ff<=2'b01;end

else if(key1==0&&key10==1&&key100==0) begin gate<=clk_100hz;ff<=2'b10;end

else if(key1==0&&key10==0&&key100==1) begin gate<=clk_1khz;ff<=2'b11;end

else begin ff<=0;end end end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

always @(posedge gate) begin

count<=count+1; if (count<=9)

begin gate_out1<=1;clk_clear<=0;clk_latch<=0;end else if (count==11)

begin gate_out1<=0;clk_clear<=0;clk_latch<=1;end else if (count==13)

begin gate_out1<=0;clk_clear<=1;clk_latch<=0;count<=0;end else

begin gate_out1<=0;clk_clear<=0;clk_latch<=0;end end

endmodule

仿真图

仿真模块

三, 计数器程序

module counter(rest,start,clk_in,cnt1,cnt2,cnt3,cnt4,cnt5,cnt6,yichu,clk_clear); input rest,start,clk_in,clk_clear;

output yichu; reg yichu;

output reg [4:1]cnt1,cnt2,cnt3,cnt4,cnt5,cnt6;

initial begin yichu=1;

cnt1<=4'b0000;cnt2<=4'b0000;cnt3<=4'b0000;cnt4<=4'b0000; cnt5<=4'b0000; cnt6<=4'b0000;

end

always@(posedge clk_in ) begin

if(!rest) begin

cnt1<=4'b0000;cnt2<=4'b0000;cnt3<=4'b0000; cnt4<=4'b0000;cnt5<=4'b0000;cnt6<=4'b0000; end else begin

if(clk_clear==1) begin

cnt1<=4'b0000;cnt2<=4'b0000;cnt3<=4'b0000;

cnt4<=4'b0000;cnt5<=4'b0000;cnt6<=4'b0000;yichu<=1; end else if(start==1) begin