基于Verilog的数字频率计的设计包含代码及仿真

if((cnt6==4'b1001)&&(cnt5==4'b1001)&&(cnt4==4'b1001)&&(cnt3==4'b1001)&&(cnt2==4'b1001)&&(cnt1==4'b1001))

begin

cnt1<=4'b0000;cnt2<=4'b0000; cnt3<=4'b0000;cnt4<=4'b0000;

cnt5<=4'b0000;cnt6<=4'b0000; yichu<=0;

end

else

if((cnt5==4'b1001)&&(cnt4==4'b1001)&&(cnt3==4'b1001)&&(cnt2==4'b1001)&& (cnt1==4'b1001))

begin

cnt1<=4'b0000;cnt2<=4'b0000;

cnt3<=4'b0000;cnt4<=4'b0000;

cnt5<=4'b0001;cnt6<=cnt6+4'b0001; end

else

if((cnt4==4'b1001)&&(cnt3==4'b1001)&&(cnt2==4'b1001)&&(cnt1==4'b1001)) begin

cnt1<=4'b0000;cnt2<=4'b0000;cnt3<=4'b0000;

cnt4<=4'b0000;cnt5<=cnt5+4'b0001;cnt6<=cnt6; end

else if((cnt3==4'b1001)&&(cnt2==4'b1001)&&(cnt1==4'b1001)) begin

cnt1<=4'b0000;cnt2<=4'b0000;cnt3<=4'b0000;

cnt4<=cnt4+4'b0001;cnt5<=cnt5;cnt6<=cnt6;

end

else if((cnt2==4'b1001)&&(cnt1==4'b1001)) begin

cnt1<=4'b0000;cnt2<=4'b0000;

cnt3<=cnt3+4'b0001;

cnt4<=cnt4;cnt5<=cnt5;cnt6<=cnt6; end

else if((cnt1==4'b1001)) begin

cnt1<=4'b0000;cnt2<=cnt2+4'b0001;cnt3<=cnt3; cnt4<=cnt4;cnt5<=cnt5;cnt6<=cnt6; end

else begin

cnt1<=cnt1+4'b0001;cnt2<=cnt2;cnt3<=cnt3; cnt4<=cnt4;cnt5<=cnt5;cnt6<=cnt6; end end

end

end

endmodule

仿真图

模块仿真图

四，锁存以及译码扫描显示程序

module v138(rest,clk_1khz,se,in1,in2,in3,in4,in5,in6,segs,ff,dp,led,en,clk_latch);

input [4:1] in1,in2,in3,in4,in5,in6; input clk_1khz,rest; input [2:1]ff; input clk_latch;

output reg dp, led,en; output reg [4:1] se; reg [3:1] count,dig; output reg [7:1] segs; reg [4:1] sign_out4;

reg [4:1] latch1,latch2,latch3,latch4,latch5,latch6;

initial begin count<=0; dp<=1 ;segs<=0;

se<=0;sign_out4<=0;led<=0;en<=0; latch1<=0;latch2<=0;latch3<=0; latch4<=0;latch5<=0;latch6<=0; end

////////////////////////////////////////////////////////////////////////////////////

always@( posedge clk_latch )

begin

latch1<=in1;latch2<=in2;latch3<=in3; latch4<=in4;latch5<=in5;latch6<=in6; end

/////////////////////////////////////////////////////////////////////////////////锁存器。 always@(posedge clk_1khz) begin

count<=count+1; end

/////////////////////////////////////////////////////////////////////////////////位选自加 always@(posedge clk_1khz ) begin

if(!rest)

begin led<=1; end