FPGA可编程逻辑器件芯片EP1S20F780I7中文规格书 - 图文

PLL

Specifications

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See the DC & Switching Characteristics chapter in volume 1 of the StratixIIGX Device Handbook (or the StratixII Device Handbook) for information about PLL timing specifications

StratixII and Stratix II GX devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock-management solution.

Clocking

Global and Hierarchical Clocking

StratixII and Stratix II GX devices provide 16 dedicated global clock networks and 32 regional clock networks. These clocks are organized into a hierarchical clock structure that allows for 24 unique clock sources per device quadrant with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains within the entire StratixII or Stratix II GX device. Table1–17 lists the clock resources available on StratixII devices.

There are 16 dedicated clock pins (CLK[15..0]) on StratixII and

StratixIIGX devices to drive either the global or regional clock networks. Four clock pins drive each side of the StratixII device, as shown in

Figures1–39 and 1–40. Enhanced and fast PLL outputs can also drive the global and regional clock networks.

Table1–17.Clock Resource Availability in StratixII and Stratix II GX Devices(Part 1 of2)

Description

Number of clock input pinsNumber of regional clock networks

Global clock input sourcesRegional clock input sources

24 32

Clock input pins, PLL outputs, logic array

Clock input pins, PLL outputs, logic array

Number of global clock networks16

StratixII Device AvailabilityStratixII GX Device Availability

12 1632

Clock input pins, PLL outputs, logic array, inter-transceiver clocksClock input pins, PLL outputs, logic array, inter-transceiver clocks24 (16 GCLK and 8 RCLK clocks)

Number of unique clock sources 24 (16 global clocks and 8 regional in a quadrantclocks)

Number of unique clock sources 48 (16 global clocks and 32 regional 48 (16 GCLK and 32 RCLK clocks)in the entire deviceclocks)Stratix II Device Handbook, Volume 2

Clocking

The clock input multiplexer control signals for performing clock switchover are from core signals. Figure1–44 shows the clock input multiplexer control circuit for a center fast PLL. Figure1–44.Center Fast PLL Clock Input Multiplexer Control

(1)core_inclkclk[3..0]4inclk0To the ClockSwitchoverBlockinclk1core_inclk(1)Note to Figure1–44: (1)

The input clock multiplexing is controlled through a configuration file only and cannot be dynamically controlled in user mode.

Stratix II Device Handbook, Volume 2

PLLs in StratixII and StratixIIGX Devices

Delay Compensation for Fast PLLs

Each center fast PLL can be fed by any one of four possible input clock pins. Among the four clock input signals, only two are fully

compensated, i.e., the clock delay to the fast PLL matches the delay in the data input path when used in the LVDS receiver mode. The two clock inputs that match the data input path are located right next to the fast PLL. The two clock inputs that do not match the data input path are located next to the neighboring fast PLL. Figure1–46 shows the above description for the left-side center fast PLL pair. If the PLL is used in non-LVDS modes, then any of the four dedicated clock inputs can be used and are compensated.

Fast PLL 1 and PLL 2 can choose among CLK[3..0] as the clock input source. However, for fast PLL 1, only CLK0 and CLK1 have their delay matched to the data input path delay when used in the LVDS receiver mode operation. The delay from CLK2 or CLK3 to fast PLL 1 does not match the data input delay. For fast PLL 2, only CLK2 and CLK3 have their delay matched to the data input path delay in LVDS receiver mode

operation. The delay from CLK0 or CLK1 to fast PLL 2 does not match the data input delay. The same arrangement applies to the right side center fast PLL pair. For corner fast PLLs, only the corner FPLLCLK pins are fully compensated. For LVDS receiver operation, it is recommended to use the delay compensated clock pins only.

Figure1–46.Delay Compensated Clock Input Pins for Center Fast PLL Pair

CLK0CLK1Fast PLL 1Fast PLL 2CLK2CLK3Stratix II Device Handbook, Volume 2

Clocking

Figure1–49.Stratix II GX Center Fast PLLs, Clock Pin and Logic Array Signal Connectivity to Global and Regional Clock NetworksNotes(1) and (2)

CLK0CLK1FastPLL 1C0C1C2C3Logic ArraySignal InputTo ClockNetworkC0CLK2CLK3FastPLL 2C1C2C3RCK0RCK1RCK2RCK3RCK4RCK5RCK6RCK7GCK0GCK1GCK2GCK3Notes to Figure1–49:(1)(2)

The redundant connection dots facilitate stitching of the clock networks to support the ability to drive two quadrants with the same clock.

The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. The global or regional clock inputcan be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.

Stratix II Device Handbook, Volume 2

PLLs in StratixII and StratixIIGX Devices

The global and regional clock networks that are not used are

automatically powered down through configuration bit settings in the configuration file (SRAM Object File (.sof) or Programmer Object File (.pof)) generated by the QuartusII software.

The dynamic clock enable or disable feature allows the internal logic to control power up or down synchronously on GCLK and RCLK nets,

including dual-regional clock regions. This function is independent of the PLL and is applied directly on the clock network, as shown in Figure1–52 on page1–87 and Figure1–53 on page1–88.

The input clock sources and the clkena signals for the global and regional clock network multiplexers can be set through the QuartusII software using the altclkctrl megafunction. The dedicated external clock output pins can also be enabled or disabled using the altclkctrl megafunction. Figure1–54 shows the external PLL output clock control block.

Figure1–54.Stratix II External PLL Output Clock Control Block

PLL CounterOutputs (c[5..0])6Static Clock Select(1)Enable/DisableInternalLogicIOE(2)InternalLogicStatic ClockSelect(1)PLL_OUTPinNotes to Figure1–54:(1)(2)

These clock select signals can only be set through a configuration file and cannot be dynamically controlled during user mode operation.

The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.

Stratix II Device Handbook, Volume 2