硬件描述语言cpld程序

module test2(DB,AB,RESET,DSP_RST,C_OE,C_DIR,AOE,AWE,ARE,RW,FCE,INT0,CE1,CE2, WR_7226,CHAN_OC,CHAN_C,ALE_ST,ADC_OE,ADC_CLK,CLKIN,test, LED_OC1,LED_C1,LED_OC2,LED_C2,LED_OC3,LED_C3, FA14,FA15,FA16,FA17,FA18,FA19, PORT0,PORT1); input [7:0] DB; input [7:0] AB; output [7:0] test;

input RESET,AOE,AWE,ARE,RW,FCE,INT0,CE1,CE2,CLKIN; output DSP_RST,C_OE,C_DIR,FA14,FA15,FA16,FA17,FA18,FA19; output LED_OC1,LED_C1,LED_OC2,LED_C2,LED_OC3,LED_C3; output WR_7226,CHAN_OC,CHAN_C,ALE_ST,ADC_OE,ADC_CLK; output PORT0,PORT1;

reg PORT0,PORT1; reg C_OE,C_DIR;

reg LED_OC1,LED_C1,LED_OC2,LED_C2,LED_OC3,LED_C3; reg WR_7226,CHAN_OC,CHAN_C,ALE_ST,ADC_OE,ADC_CLK; reg [7:0] counter=0; reg CLK;

reg [7:0] test=0;

assign DSP_RST = RESET;

always @ (AB) begin

case(AB)

8'd1: begin C_OE=0; C_DIR=1; LED_OC1=0; LED_C1=1;

8'd2: begin C_OE=0; C_DIR=1; LED_OC2=0; LED_C2=1; 8'd3: begin C_OE=0; C_DIR=1; LED_OC3=0; LED_C3=1; 8'd4: begin CHAN_C=1; 8'd5: begin CHAN_C=0; 8'd6: begin WR_7226=0; 8'd7: begin WR_7226=1; 8'd8: begin C_OE=0; C_DIR=0; ALE_ST=1; ADC_OE=0; 8'd9: begin C_OE=0; C_DIR=0; ALE_ST=1; ADC_OE=1; 8'd10: begin ADC_CLK=CLKIN; end

8'd11: begin C_OE=0; C_DIR=1; LED_OC1=0; LED_C1=0; 8'd12: begin C_OE=0; C_DIR=1; LED_OC3=0; LED_C3=0; 8'd13: begin C_OE=0; C_DIR=1; LED_OC3=0; LED_C3=0; end end end end end end end end end end end end

8'd14: begin C_OE=0; C_DIR=0; end

8'd15: begin C_OE=0; C_DIR=1; PORT0=0; PORT1=1; end

default: begin C_OE=0; C_DIR=1; LED_OC1=1;LED_OC2=1; LED_OC3=1; PORT0=1; CHAN_OC=0; CHAN_C=0; WR_7226=1; ALE_ST=0; ADC_OE=0;end endcase

end

//////////////////////////////////////////////////////////// always @ (posedge CLKIN)

begin

if(counter==255)

begin counter=0; CLK= ~CLK; end else counter=counter+1; end

//////////////////////////////////////////////////////////// always @ (AB) begin test = AB; end

/////////////////////////////// endmodule