output begins at the column address last specified in the READ PAGE (00h-30h) com-mand. The RANDOM DATA READ TWO-PLANE (06h-E0h) command is used to enabledata output in the other cache registers.
Figure 38: READ PAGE (00h-30h) Operation
Cycle typeCommandAddressAddressAddressAddressAddressCommandDOUTDOUTDOUTI/O[7:0]00hC1C2R1R2R330htWBtRtRRDnDn+1Dn+2RDYFigure 39: READ PAGE (00h-30h) Operation with Internal ECC Enabled
tR_ECCRDYI/O[7:0]00hAddressAddressAddressAddressAddress30h70hStatus00hDOUT (serial access)SR bit 0 = 0 READ successfulSR bit 1 = 0 READ error
READ PAGE CACHE SEQUENTIAL (31h)
The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential pagewithin a block into the data register while the previous page is output from the cacheregister. This command is accepted by the die (LUN) when it is ready
(RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE(31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue this command, write 31h to the command register. After this command is is-sued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. AftertRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation
(RDY = 1, ARDY = 0), indicating that the cache register is available and that the specifiedpage is copying from the NAND Flash array to the data register. At this point, data canbe output from the cache register beginning at column address 0. The RANDOM DATAREAD (05h-E0h) command can be used to change the column address of the data beingoutput from the cache register.
The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block
boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after thelast page of a block is read into the data register, the next page read will be the next logi-cal block in which the 31h command was issued. Do not issue the READ PAGE CACHESEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGECACHE LAST (3Fh) command.
PDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Two-Plane Operations
Figure 70: TWO-PLANE PAGE READ
CLE
WE#
ALE
RE#
Page address MPage address MRowadd 3I/Ox00hColadd 1Coladd 2Rowadd 1Rowadd 200hColadd 1Coladd 2Rowadd 1Rowadd 2Rowadd 330htRColumn address JR/B#
Plane 0 addressColumn address JPlane 1 address1CLEWE#ALERE#I/OxDOUT 0DOUT 1DOUTPlane 0 data06hColadd 1Coladd 2Rowadd 1Rowadd 2Rowadd 3E0hDOUT 0DOUT 1DOUTPlane 1 dataPlane 1 addressR/B#1Notes:
1.Column and page addresses must be the same.
2.The least significant block address bit, BA6, must be different for the first- and second-plane addresses.
PDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Two-Plane Operations
Figure 71: TWO-PLANE PAGE READ with RANDOM DATA READ
tRR/B#RE#I/Ox00hAddress (5 cycles)00hPlane 0 addressAddress (5 cycles)30hPlane 1 addressData outputPlane 0 data05hAddress(2 cycles)E0hData outputPlane 0 data1
R/B#RE#I/Ox06hAddress (5 cycles)E0hPlane 1 addressData outputPlane 1 data05hAddress(2 cycles)E0hData outputPlane 1 data1
Figure 72: TWO-PLANE PROGRAM PAGE
tDBSYtPROGR/B#I/Ox80hAddress (5 cycles)Data input11h1st-plane address
80hAddress (5 cycles)2nd-plane address
Data input10h70hStatusPDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Two-Plane Operations
tDBSYR/B#
I/Ox80hAddress (5 cycles)1st-plane addressData input85hAddress (2 cycles)Data input11h80hAddress (5 cycles)2nd-plane addressData inputDifferent column address than previous 5 address cycles, for 1st plane onlyUnlimited number of repetitions1PDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Two-Plane Operations
Figure 74: TWO-PLANE PROGRAM PAGE CACHE MODE
tDBSYtCBSYR/B#
I/Ox80hAddress/data input1st plane11h80hAddress/data input2nd plane15h1
tDBSYtCBSYR/B#
I/Ox80hAddress/data input1st plane11h80hAddress/data input2nd plane15h12tDBSYtLPROGR/B#
I/Ox80hAddress/data input1st plane11h80hAddress/data input2nd plane10h2
PDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
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