基于VHDL的数字闹钟设计 - 图文

附录

signal counter:std_logic_vector(1 downto 0); signal tmp,sig1,sig2:std_logic; begin

sig2<=key_pre;

tmp<=row(0) and row(1) and row(2) and row(3); process(clky) begin

if(clky'event and clky='1')then --计数进程 if(sig2='1')then

if(counter=\ sig1<='0';

counter<=\ else

sig1<='1';

counter<=counter+'1'; end if; else

sig1<=’0’;

counter<=”00”; end if; end if;

end process;

process(clky) variable jt :std_logic; begin

if(clky'event and clky='1')then if(sig1='1')then jt:=sig_com(3);

for i in 3 downto 1 loop

sig_com(i)<=sig_com(i-1); end loop;

sig_com(0)<=jt; else

sig_com<=\ end if; end if;

end process; process(clky) begin

if(clky'event and clky='1')then if(sig1='1')then com<=sig_com; else

com<=\ end if; end if;

end process;

process(clky) begin

if(clky'event and clky='1')then

--列线逐位输出低电平 --键码信号赋值 25

附 录

if(sig1='1')then if(tmp='0')then

scan_code<=row & sig_com; else

scan_code<=\ end if; else

scan_code<=\ end if; end if;

end process; end behav;

（6）顶层电路设计

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY clock IS

PORT ( CLK12MHZ : IN STD_LOGIC; CLK8HZ : IN STD_LOGIC; SPKOUT : OUT STD_LOGIC; CLK : IN STD_LOGIC; KEY1 : IN STD_LOGIC;

KEY2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); H1,H2,M1,M2,S1,S2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END;

ARCHITECTURE one OF clock IS COMPONENT shizhong

PORT (clk : in std_logic; md1 : in std_logic;

md2 : in std_logic_vector(1 downto 0); clken : out std_logic;

h1,h2,m1,m2,s1,s2: out std_logic_vector(3 downto 0)); END COMPONENT; COMPONENT NoteTabs

PORT ( clk : IN STD_LOGIC;

ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT; COMPONENT ToneTaba

PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; Tone : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); en : in std_logic); END COMPONENT; COMPONENT Speakera

PORT ( clk : IN STD_LOGIC;

Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC ); END COMPONENT;

SIGNAL Tone :STD_LOGIC_VECTOR (10 DOWNTO 0); SIGNAL ToneIndex :STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL clken :STD_LOGIC;

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附录

SIGNAL en :STD_LOGIC; BEGIN

u1 : Shizhong PORT MAP (clk=>CLK,md1=>KEY1,md2=>KEY2,clken=>en,

h1=>h1,h2=>h2,m1=>m1,m2=>m2,s1=>s1,s2=>s2);

u2 : NoteTabs PORT MAP (clk=>CLK8HZ, ToneIndex=>ToneIndex); u3 : ToneTaba PORT MAP (Index=>ToneIndex,Tone=>Tone,en=>en);

u4 : Speakera PORT MAP (clk=>CLK12MHZ,Tone=>Tone, SpkS=>SPKOUT ); END;

附录2 动态扫描模块程序

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity seltime is

port(disclk,conv:in std_logic;

m0,m1,f0,f1,s0,s1,r0,r1,y0,y1,n0,n1,n2,n3:in std_logic_vector(3 downto 0); dataout:out std_logic_vector(3 downto 0); wsel:out std_logic_vector(3 downto 0)); end seltime;

architecture st of seltime is

signal count:std_logic_vector(3 downto 0); begin

wsel<=count;

process(disclk,conv) begin

if disclk'event and disclk='1' then if count>=\ count<=\ else

count<=count+1; end if; end if; if conv='1' then case count is

when\ when\ when\ when\ when\ when\ when others =>dataout<=\ end case; else

case count is

when\ when\

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when\ when\ when\ when\ when\ when\

when others =>dataout<=\ end case; end if; end process; end st;

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