Symbol
TIOTPHZ
Description
T input to Pad high-impedance
Speed Grade
-2I1.01
-1I1.12
-1M1.12
Unitsns
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table58 shows the test setup parameters used for measuring input delay.Table 58:Input Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)LVCMOS (Low-Voltage CMOS), 3.3VLVCMOS, 2.5VLVCMOS, 1.8VLVCMOS, 1.5VLVCMOS, 1.2V
PCI (Peripheral Component Interconnect), 33 MHz, 3.3V
PCI, 66 MHz, 3.3VPCI-X, 133 MHz, 3.3VGTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I & IIHSTL, Class III & IVHSTL, Class I & II, 1.8VHSTL, Class III & IV, 1.8V
SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V
SSTL, Class I & II, 2.5VSSTL, Class I & II, 1.8V
AGP-2X/AGP (Accelerated Graphics Port)LVDS (Low-Voltage Differential Signaling), 2.5VLVDSEXT (LVDS Extended Mode), 2.5VLDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5VNotes:
1.2.3.4.5.6.
The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delaymeasurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all otherDCI standards are the same for the corresponding non-DCI standards.Input waveform switches between VL and VH.
Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREFvalues listed are typical.
Input voltage level from which measurement starts.
This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure11,page35.
The value given is the differential input voltage.
I/O Standard AttributeLVTTL
LVCMOS33LVCMOS25LVCMOS18LVCMOS15LVCMOS12PCI33_3PCI66_3PCIXGTL
GTLP
HSTL_I, HSTL_IIHSTL_III, HSTL_IVHSTL_I_18, HSTL_II_18HSTL_III_18, HSTL_IV_18SSTL3_I,SSTL3_IISSTL2_I,SSTL2_IISSTL18_I,SSTL18_IIAGPLVDS_25LVDSEXT_25 LDT_25LVPECL_25
VL(1)(2)
000000
VH(1)(2)
VMEAS
(1)(4)(5)VREF(1)(3)(5)–––––––––3.01.43.31.652.51.251.80.91.50.751.20.6
Per PCI? SpecificationPer PCI SpecificationPer PCI-X? SpecificationVREF–0.2VREF–0.2VREF–0.5VREF–0.5VREF–0.5VREF–0.5VREF–1.00VREF–0.75VREF–0.5VREF– (0.2xVCCO)1.2–0.1251.2–0.1250.6–0.1251.15–0.3
VREF+0.2VREF+0.2VREF+0.5VREF+0.5VREF+0.5VREF+0.5VREF+1.00VREF+0.75VREF+0.5VREF+ (0.2xVCCO)1.2+0.1251.2+0.1250.6+0.1251.15–0.3
VREFVREFVREFVREFVREFVREFVREFVREFVREFVREF0(6)0(6)0(6)0(6)
0.801.00.750.900.901.081.51.250.90AGP Spec
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (<1pF) across approximately 4\microstrip trace. Standard termination was used for all testing. The propagation delay of the 4\
characterized separately and subtracted from the final measurement, and is therefore not included in the
generalized test setups shown in Figure11 and Figure12.
X-Ref Target - Figure 11X-Ref Target - Figure 12FPGA Output+CREFRREFVMEAS–ds714_12_012109VREFFigure 12:Differential Test Setup
Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it.
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method:
1.Simulate the output driver of choice into the generalized
test setup, using values from Table59.2.Record the time to VMEAS.
3.Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or capacitance value to represent the load.4.Record the time to VMEAS.
5.Compare the results of step2 and step4. The increase
or decrease in delay yields the actual propagation delayof the PCB trace.
FPGA OutputRREFVMEAS(voltage level when taking delay measurement)CREF (probe capacitance)DS714_11_012109Figure 11:Single Ended Test Setup
Table 59:Output Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)LVCMOS (Low-Voltage CMOS), 3.3VLVCMOS, 2.5VLVCMOS, 1.8VLVCMOS, 1.5VLVCMOS, 1.2V
PCI (Peripheral Component Interface), 33 MHz, 3.3VPCI, 66 MHz, 3.3VPCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)GTL Plus
HSTL (High-Speed Transceiver Logic), Class IHSTL, Class IIHSTL, Class III
DS714 (v2.2) January 17, 2011Product Specification
I/O StandardAttribute
LVTTL (all)LVCMOS33LVCMOS25LVCMOS18LVCMOS15LVCMOS12
PCI33_3 (rising edge)PCI33_3 (falling edge)PCI66_3 (rising edge)PCI66_3 (falling edge)PCIX (rising edge)PCIX (falling edgeGTLGTLPHSTL_IHSTL_IIHSTL_III
RREF (?)1M1M1M1M1M1M2525252525252525502550
CREF(1)(pF)00000010(2)10(2)10(2)10(2)10(3)10(3)00000
VMEAS(V)1.41.651.250.90.750.60.942.030.942.030.942.030.81.0VREFVREF0.9
VREF(V)00000003.303.33.31.21.50.750.751.5
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 68:Block RAM and FIFO Switching Characteristics
Symbol
Block RAM and FIFO Clock to Out DelaysTRCKO_DO and TRCKO_DOR(1)
Clock CLK to DOUT output (without output register)(2)(3)Clock CLK to DOUT output (with output register)(4)(5)Clock CLK to DOUT output with ECC (without output register)(2)(3)
Clock CLK to DOUT output with ECC (with output register)(4)(5)
Clock CLK to DOUT output with Cascade (without output register)(2)
Clock CLK to DOUT output with Cascade (with output register)(4)
TRCKO_FLAGSTRCKO_POINTERSTRCKO_ECCRTRCKO_ECC
Clock CLK to FIFO flags outputs(6)Clock CLK to FIFO pointer outputs(7)Clock CLK to BITERR (with output register)Clock CLK to BITERR (without output register)Clock CLK to ECCPARITY in standard ECC modeClock CLK to ECCPARITY in ECC encode only mode
1.920.693.030.772.441.070.871.260.772.851.470.89
2.190.823.610.932.941.301.021.480.933.411.741.05
2.190.823.610.932.941.301.021.480.933.411.741.05
ns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Max
Description
Speed Grade-2I
-1I
-1M
Units
Setup and Hold Times Before/After Clock CLKTRCCK_ADDR/TRCKC_ADDRTRDCK_DI/TRCKD_DI
ADDR inputs(8)DIN inputs(9)
DIN inputs with ECC in standard mode(9)
TRDCK_DI_ECC/TRCKD_DI_ECC
DIN inputs with ECC encode only(9)
TRCCK_EN/TRCKC_EN
TRCCK_REGCE/TRCKC_REGCETRCCK_SSR/TRCKC_SSRTRCCK_WE/TRCKC_WETRCCK_WREN/TRCKC_WREN
Block RAM Enable (EN) inputCE input of output register
Synchronous Set/ Reset (SSR) inputWrite Enable (WE) input WREN/RDEN FIFO inputs(10)
0.400.320.300.280.370.330.720.330.360.150.160.240.210.250.510.170.410.34
0.480.360.350.290.420.360.770.360.420.150.180.270.260.280.630.180.480.40
0.480.360.350.290.420.470.770.470.420.150.180.270.260.280.630.180.480.40
ns, Minns, Minns, Minns, Minns, Minns, Minns, Minns, Minns, Min
Reset DelaysTRCO_FLAGS
Reset RST to FIFO Flags/Pointers(11)
1.26
1.48
1.48
ns, Max
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 74:PLL Specification
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011Product Specification
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