Family 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. SYMBOL
TEST CONDITIONS PARAMETER WAVEFORMS VCC (V) MIN. TYP. MAX. UNIT Tamb = 25 ?C t/tPHLPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 ? 25 42 ns propagation delay ttt ST_CP to Qn see Fig.8 4.5 ? 24 40 ns PHL PZHPZL PHZPLZ propagation delay MR to Q7’ OE to Qn OE to Qn see Fig.10 4.5 ? 23 40 ns ns /t/t 3-state output enable time see Fig.11 4.5 ? 21 35 30 3-state output disable time see Fig.11 4.5 ? 18 6 ns ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 16 16 ? storage clock pulse width HIGH or LOW see Fig.8 4.5 5 ? ns master reset pulse width t LOW see Fig.10 4.5 20 8 ? ns su set-up time DS to SH_CP see Fig.9 set-up time SH_CP to ST_CP see Fig.8 4.5 4.5 16 16 5 8 ? ? ns ns th t rem max hold time DS to SH_CP removal time MR to SH_CP see Fig.9 see Fig.10 4.5 4.5 +3 +10 ?2 ?7 ? ? ns ns MHz f maximum clock pulse frequency see Figs 7 and 8 4.5 30 52 ? SH_CP or ST_CP Tamb = ?40 to +85 ?C t/tPHLPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 ? ? 53 ns tttpropagation delay ST_CP to Qn see Fig.8 4.5 ? ? 50 ns PHL PZHPZL PHZPLZ propagation delay MR to Q7’ OE to Qn OE to Qn see Fig.10 4.5 ? ? 50 ns ns /t/t 3-state output enable time see Fig.11 4.5 ? ? 44 38 3-state output disable time see Fig.11 4.5 ? ? ns
SYMBOL PARAMETER TEST CONDITIONS WAVEFORMS VCC (V) MIN. TYP. MAX. UNIT ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 20 ? ? ? storage clock pulse width HIGH or LOW see Fig.8 4.5 20 ? ns master reset pulse width t LOW see Fig.10 4.5 25 ? ? ns su set-up time DS to SH_CP see Fig.9 set-up time SH_CP to ST_CP th tfsee Fig.8 4.5 4.5 20 20 ? ? ? ? ns ns rem max hold time DS to SH_CP removal time MR to SH_CP see Fig.9 see Fig.10 4.5 4.5 3 13 ? ? ? ? ns ns MHz maximum clock pulse frequency see Figs 7 and 8 4.5 24 ? ? SH_CP or ST_CP Tamb = ?40 to +125 ?C t/tPHLPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 ? ? 63 ns tttpropagation delay ST_CP to Qn see Fig.8 4.5 ? ? 60 ns PHL PZHPZL PHZPLZ propagation delay MR to Q7’ OE to Qn OE to Qn see Fig.10 4.5 ? ? 60 ns ns /t/t 3-state output enable time see Fig.11 4.5 ? ? 53 45 3-state output disable time see Fig.11 4.5 ? ? ? ns ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 24 24 ? storage clock pulse width HIGH or LOW see Fig.8 4.5 ? ? ns master reset pulse width t LOW see Fig.10 4.5 30 ? ? ns su set-up time DS to SH_CP see Fig.9 set-up time SH_CP to ST_CP see Fig.8 4.5 4.5 24 24 ? ? ? ? ns ns th t rem max hold time DS to SH_CP removal time MR to SH_CP see Fig.9 see Fig.10 4.5 4.5 3 15 ? ? ? ? ns ns MHz f maximum clock pulse frequency see Figs 7 and 8 4.5 20 ? ?
SH_CP or ST_CP
AC WAVEFORMS（74HC595PW）
SH_CP input
VM
1/fmax
t
Q7' output
t
tW PLH
PHL 90% 10%
VM
MSA699
t
TLH
t
THL
74HC595: VM = 50%; VI = GND to VCC.
74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock (SH_CP) to output (Q7’) propagation delays, the shift clock pulse width
and maximum shift clock frequency.
SH_CP input
V
M
t
ST_CP input
su
1/f
V
M tW
max
t
Qn output
PLH
VM
t
PHL
MSA700
74HC595: VM = 50%; VI = GND to VCC.
74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the storage clock (ST_CP) to output (Qn) propagation delays, the storage
clock pulse width and the shift clock to storage clock set-up time.
handbook, full pagewidth SH_CP input VM tsu tth su t 74HC595: VM = 50%; VI = GND to VCC. Q7' output DS input h VM VM MLB196 74HCT595: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.9 Waveforms showing the data set-up and hold times for the DS input. MR input VM tW SH_CP input trem V M Q7' output t PHL V M MLB197 74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the Master Reset (MR) pulse width, the master reset to output (Q7’) propagation delay and the master reset to shift clock (SH_CP) removal time. handbook, full pagewidth
OE input tr tf 90% 10% VM t PLZ Qn output LOW-to-OFF OFF-to-LOW t PZL M V 10% t PHZ t90% PZH Qn output HIGH-to-OFF OFF-to-HIGH disabled VM outputs enabled MSA697 74HC595: VM = 50%; VI = GND to VCC. outputs outputs enabled
74HCT595: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the 3-state enable and disable times for input OE. handbook, full pagewidth
V
GENERATOR
PULSE
VCC
VV
O
CC
I
D.U.T
RL = 1 k?
R
T
C
L
50 pF
MGK563
TEST tPLH/tPHL
SWITCH
open
Definitions for test circuit: RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
tPLZ/tPZL tPHZ/tPZH
V
CC GND
Fig.12 Test circuit for 3-state outputs.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
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