Spartan-3 FPGA Family: Pinout Descriptions
Table 80:Bitstream Options Affecting Spartan-3 Device Pins (Cont’d)
Affected Pin Name(s)CCLKCCLKPROG_B
Bitstream Generation Function
After configuration, this bitstream option either pulls CCLK to VCCAUX via a pull-up resistor, or allows CCLK to float.
For Master configuration modes, this option sets the approximate frequency, in MHz, for the internal silicon oscillator.
A pull-up resistor to VCCAUX exists on PROG_B during configuration. After configuration, this bitstream option either pulls PROG_B to VCCAUX via a pull-up resistor, or allows PROG_B to float.
After configuration, this bitstream option either pulls DONE to VCCAUX via a pull-up resistor, or allows DONE to float. See also DriveDone option.If set to Yes, this option allows the FPGA’s DONE pin to drive High when configuration completes. By default, the DONE is an open-drain output and can only drive Low. Only single FPGAs and the last FPGA in a multi-FPGA daisy-chain should use this option.
After configuration, this bitstream option either pulls M2 to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows M2 to float.After configuration, this bitstream option either pulls M1 to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows M1 to float.After configuration, this bitstream option either pulls M0 to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows M0 to float.After configuration, this bitstream option either pulls HSWAP_EN to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows HSWAP_EN to float.
After configuration, this bitstream option either pulls TDI to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows TDI to float.After configuration, this bitstream option either pulls TMS to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows TMS to float.After configuration, this bitstream option either pulls TCK to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows TCK to float.After configuration, this bitstream option either pulls TDO to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows TDO to float.
Option Variable NameCclkPinConfigRateProgPin
Values (Default)?Pullup?Pullnone?3, 6, 12, 25,50?Pullup?Pullnone?Pullup?Pullnone?No?Yes
DONEDONE
DonePinDriveDone
M2M2Pin
?Pullup?Pulldown?Pullnone?Pullup?Pulldown?Pullnone?Pullup?Pulldown?Pullnone?Pullup?Pulldown?Pullnone?Pullup?Pulldown?Pullnone?Pullup?Pulldown?Pullnone?Pullup?Pulldown?Pullnone?Pullup?Pulldown?Pullnone
M1M1Pin
M0M0Pin
HSWAP_ENHswapenPin
TDITdiPin
TMSTmsPin
TCKTckPin
TDOTdoPin
Setting Bitstream Generator Options
Refer to the “BitGen” chapter in the Xilinx ISE? software documentation.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
Package Overview
Table81 shows the 10 low-cost, space-saving production package styles for the Spartan-3 family. Each package style is available as a standard and an environmentally-friendly lead-free (Pb-free) option. The Pb-free packages include an extra ‘G’ in the package style name. For example, the standard \Pb-free option. The mechanical dimensions of the standard and Pb-free packages are similar, as shown in the mechanical drawings provided in Table83.
Not all Spartan-3 device densities are available in all packages. However, for a specific package there is a common footprint that supports the various devices available in that package. See the footprint diagrams that follow.Table 81:Spartan-3 Family Package Options
PackageVQ100 / VQG100CP132 / CPG132(1)TQ144 / TQG144PQ208 / PQG208FT256 / FTG256FG320 / FGG320FG456 / FGG456FG676 / FGG676FG900 / FGG900FG1156 / FGG1156(1)
Leads1001321442082563204566769001156
Type
Very-thin Quad Flat PackChip-Scale PackageThin Quad Flat PackQuad Flat Pack
Fine-pitch, Thin Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid Array
Maximum
I/O
638997141173221333489633784
Pitch (mm)0.50.50.50.51.01.01.01.01.01.0
Footprint(mm)16 x 168 x 822 x 2230.6 x 30.617 x 1719 x 1923 x 2327 x 2731 x 3135 x 35
Height (mm)1.201.101.604.101.552.002.602.602.602.60
Characteristic
Maximum User I/O
Packing Density (Logic/Area)Signal Integrity
Simultaneous Switching Output (SSO) SupportThermal Dissipation
Minimum Printed Circuit Board (PCB) LayersHand Assembly/Rework
Quad Flat-Pack (QFP)
141GoodFairLimitedFair4Possible
Ball Grid Array (BGA)
633BetterBetterBetterBetter6Very Difficult
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013Product Specification
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