end state2_spe_01: if(switch[1]==0) begin
state2<=state2_spe_02; count2<=39; end
else state2<=state2_spe_01;
state2_spe_02: if(count2>0) begin
count2<=count2-1; end else
state2<=state2_neg; state2_neg: begin
light[1]<='b0; state2<=IDLE2; counter2<=3'b0; end state2_pos: begin
light[1]<='b1; state2<=state2_main; end
default:state2=IDLE2; endcase /*
The third always block!!!To deal with light3&switch3!!! */
always@(posedge clk10) if(!rst) begin
state3<=IDLE3; count3<=8'b0; counter3<=3'b0; end else
if(switch[2]==1'b1&&counter3<5)counter3<=counter3+1; else case(state3) IDLE3:
if(switch[2]=='b1) begin
state3<=state3_pos; count3<=79; end else begin
state3<=IDLE3; light[2]=0;
end
state3_main: if(count3>0) begin
count3<=count3-1; end else
if(switch[2]==0) begin
state2<=state3_neg; end else
if(switch[2]==1) begin
state3<=state3_spe_01; end state3_spe_01: if(switch[2]==0) begin
state3<=state3_spe_02; count3<=39; end
else state3<=state3_spe_01;
state3_spe_02:
if(count3>0) begin
count3<=count3-1; end else
state3<=state3_neg; state3_neg: begin
light[1]<='b0; state3<=IDLE3; counter3<=3'b0; end state3_pos: begin
light[2]<='b1; state3<=state3_main; end
default:state3<=IDLE3; endcase endmodule
五．综合仿真结果
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