简单CPU系统设计与实现

北京邮电大学数字电路与逻辑设计实验报告

mbr_in:in std_logic_vector(11 downto 0); mbr_e:in std_logic;

ctrl:in std_logic_vector(3 downto 0); overflow:out std_logic;

acc:out std_logic_vector(11 downto 0) ); end ALU;

architecture behave of ALU is begin

process(clk,rst)

variable br: std_logic_vector(11 downto 0); variable data_acc:std_logic_vector(11 downto 0); begin

if(clk'event and clk='1')then if(rst='1')then acc<=\ br:=\ data_acc:=\ elsif(mbr_e='1')then

北京邮电大学数字电路与逻辑设计实验报告

br:=mbr_in; else null; end if; case ctrl is

when\ data_acc:=\ when\ when\

when\ when\ when\ when\ when\

when others=>null; end case; end if; acc<=data_acc;

overflow<=data_acc(11); end process; end behave;

北京邮电大学数字电路与逻辑设计实验报告

4.4 MAR (地址寄存器)

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity MAR is port (

clk:in std_logic; rst:in std_logic;

mbr_low:in std_logic_vector(7 downto 0); mbr_e:in std_logic; add:in std_logic;

mar:out std_logic_vector(7 downto 0) ); end MAR;

北京邮电大学数字电路与逻辑设计实验报告

architecture behave of MAR is begin process(clk,rst)

variable pc:std_logic_vector(7 downto 0); variable mar_mid:std_logic_vector(7 downto 0); begin

if(clk'event and clk='1')then if(rst='1')then pc:=\ mar_mid:=\ elsif(mbr_e='1')then pc:=mar_mid; mar_mid:=mbr_low; elsif(add='1')then pc:=pc+1; mar_mid:=pc; else null; end if; end if; mar<=mar_mid; end process; end behave;