简单CPU系统设计与实现

北京邮电大学数字电路与逻辑设计实验报告

4.5 MBR (缓冲寄存器)

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity MBR is port (

clk:in std_logic;

ram_in:in std_logic_vector(11 downto 0); acc_in:in std_logic_vector(11 downto 0); ram_e:in std_logic; acc_e:in std_logic; rst:in std_logic;

mbr:out std_logic_vector(11 downto 0) );

北京邮电大学数字电路与逻辑设计实验报告

end MBR;

architecture behave of MBR is begin process(clk,rst) begin

if(clk'event and clk='1')then if(rst='1')then

mbr<=\ elsif(acc_e='1')then mbr<=acc_in; elsif(ram_e='1')then mbr<=ram_in; else null; end if; end if; end process; end behave;

4.6 RAM(随机存取存储器)

北京邮电大学数字电路与逻辑设计实验报告

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity RAM is port (

clk_ram:in std_logic; w_r:in std_logic; code_e:in std_logic;

mbr_in:in std_logic_vector(11 downto 0); mar_in:in std_logic_vector(7 downto 0); ram_in:in std_logic_vector(7 downto 0); ram_out:out std_logic_vector(11 downto 0); ram_outt:out std_logic_vector(7 downto 0) ); end RAM;

北京邮电大学数字电路与逻辑设计实验报告

architecture behave of RAM is begin

process(clk_ram)

type table is array(0 to 20)of std_logic_vector(11 downto 0); variable ram:table;

variable i:integer range 0 to 31:=0; variable j:std_logic:='0'; variable code_e1:std_logic; begin

if(clk_ram'event and clk_ram='1')then if(code_e='1' and code_e1='0' and j='0')then ram(i)(11 downto 8):=ram_in(3 downto 0); ram_outt(7 downto 4)<=\

ram_outt(3 downto 0)<=ram(i)(11 downto 8); j:='1';

elsif(code_e='1' and code_e1='0' and j='1')then ram(i)(7 downto 0):=ram_in(7 downto 0); ram_outt<=ram(i)(7 downto 0); j:='0'; i:=i+1;