OSCILLATOR CIRCUIT
The DS1302 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 1 shows a functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second.
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Figure 2 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for detailed information.
Table 1. Crystal Specifications*
PARAMETER Nominal Frequency Series Resistance Load Capacitance
SYMBOL
fO ESR CL
6
MIN
TYP 32.768
45 MAX
UNITS kHz k? pF
LOCAL GROUND PLANE (LAYER 2) X1 CRYSTAL X2 NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE PACKAGE. GND COMMAND BYTE
Figure 3 shows the command byte. A command byte initiates each data transfer. The MSB (bit 7) must be a logic 1.If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1.Bits 1 to 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation(input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).
Figure 3. Address/Command Byte
716RAMCK5A44A33A22A11A00RDWRDS1302 Trickle-Charge Timekeeping Chip
CE AND CLOCK CONTROL
Driving the CE input high initiates all data transfers. The CE input serves two functions. First, CE turns on the control logic that allows access to the shift register for the address/command sequence. Second, the CE signal provides a method of terminating either single-byte or multiple-byte CE data transfer.
A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the CE input is low, all data transfer terminates and the I/O pin goes to a high-impedance state. Figure 4 shows data transfer. At power-up, CE must be a logic 0 until VCC > 2.0V. Also, SCLK must be at a logic 0 when CE is driven to a logic 1 state.
DATA INPUT
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0.
DATA OUTPUT
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as CE remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri-stated upon each rising edge of SCLK. Data is output starting with bit 0.
BURST MODE
Burst mode can be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0.
When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not.
CLOCK/CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. Table 3 illustrates the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format.
The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers the rising edge of CE.
The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second.
The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The hours data must be re-initialized whenever the 12/24 bit is changed.
DS1302 Trickle-Charge Timekeeping Chip
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………………………….-0.5Vto +7.0V Operating Temperature Range, Commercial………………………………………………………………….0°C to +70°C Operating Temperature Range, Industrial (IND)……………………………………………………………-40°C to +85°C Storage Temperature Range……………………………………………………………………………..….-55°C to +125°C Soldering Temperature (leads, 10 seconds)………………………………………………………………..………….260°C Soldering Temperature (surface mount)………………………………………………..…….See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)
PARAMETER
Supply Voltage VCC1, VCC2 Logic 1 Input Logic 0 Input
SYMBOL VCC1, VCC2 VIH VIL
VCC = 2.0V VCC = 5V
CONDITIONS (Notes 2, 10) (Note 2) (Note 2)
MIN 2.0 2.0 -0.3-0.3
TYP 3.3
MAX 5.5 VCC + 0.3 +0.3+0.8
UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)
PARAMETER
Input Leakage I/O Leakage
Logic 1 Output (IOH = -0.4mA) Logic 1 Output (IOH = -1.0mA) Logic 0 Output (IOL = 1.5mA) Logic 0 Output (IOL = 4.0mA) Active Supply Current (Oscillator Enabled) Timekeeping Current (Oscillator Enabled) Standby Current (Oscillator Disabled)
Active Supply Current (Oscillator Enabled) Timekeeping Current (Oscillator Enabled) Standby Current (Oscillator Disabled)
Trickle-Charge Resistors Trickle-Charge Diode Voltage Drop
ILI ILO VOH VOL ICC1A ICC1T ICC1S ICC2A ICC2T ICC2S R1 R2 R3 VTD
VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC1 = 2.0V VCC1 = 5V VCC1 = 2.0V VCC1 = 5V VCC1 = 2.0V VCC1 = 5V IND
VCC2 = 2.0V VCC2 = 5V VCC2 = 2.0V VCC2 = 5V VCC2 = 2.0V VCC2 = 5V
2 4 8 0.7
SYMBOL
CONDITIONS (Notes 5, 13) (Notes 5, 13) (Note 2) (Note 2) CH = 0
(Notes 4, 11) CH = 0
(Notes 3, 11,13) CH = 1
(Notes 9, 11, 13) CH = 0
(Notes 4, 12) CH = 0
(Notes 3, 12) CH = 1
(Notes 9, 12)
0.2 0.45 1 1 5
1.6 2.4
0.4 0.4 0.4 1.2 0.3 1 100 100 200 0.425 1.28 25.3 81 25 80
k?
MIN
TYP 85 85
MAX 500 500
UNITS μA μA V V mA μA nA mA μA μA
V
DS1302 Trickle-Charge Timekeeping Chip
CAPACITANCE
(TA = +25°C)
PARAMETER Input Capacitance I/O Capacitance
SYMBOL
CI CI/O
MIN
TYP 10 15
MAX
UNITS pF pF
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Data to CLK Setup CLK to Data Hold CLK to Data Delay CLK Low Time CLK High Time CLK Frequency CLK Rise and Fall CE to CLK Setup CLK to CE Hold CE Inactive Time
CE to I/O High Impedance SCLK to I/O High Impedance
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13:
(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)
SYMBOL VCC = 2.0V tDC
VCC = 5V VCC = 2.0V
tCDH
VCC = 5V VCC = 2.0V
tCDD
VCC = 5V VCC = 2.0V tCL
VCC = 5V VCC = 2.0V tCH
VCC = 5V VCC = 2.0V
tCLK
VCC = 5V VCC = 2.0V
tR, tF
VCC = 5V VCC = 2.0V tCC
VCC = 5V VCC = 2.0V
tCCH
VCC = 5V VCC = 2.0V
tCWH
VCC = 5V VCC = 2.0V
tCDZ
VCC = 5V VCC = 2.0V
tCCZ
VCC = 5V
CONDITIONS (Note 6) (Note 6) (Notes 6, 7, 8) (Note 6) (Note 6) (Note 6)
1000 250 1000 250 DC
0.5 2.0 2000 500
MIN 200 50 280 70
TYP
MAX
UNITS ns ns
800 200
ns ns ns MHz ns μs ns μs
280 70 280 70
ns ns
(Note 6) (Note 6) (Note 6) (Note 6) (Note 6)
4 1 240 60 4 1
Limits at -40°C are guaranteed by design and are not production tested. All voltages are referenced to ground.
ICC1T and ICC2T are specified with I/O open, CE and SCLK set to a logic 0.
ICC1A and ICC2A are specified with the I/O pin open, CE high, SCLK = 2MHz at VCC = 5V; SCLK = 500kHz, VCC = 2.0V. CE, SCLK, and I/O all have 40k? pulldown resistors to ground.
Measured at VIH = 2.0V or VIL = 0.8V and 10ns maximum rise and fall time. Measured at VOH = 2.4V or VOL = 0.4V. Load capacitance = 50pF.
ICC1S and ICC2S are specified with CE, I/O, and SCLK open.
VCC = VCC2, when VCC2 > VCC1 + 0.2V; VCC = VCC1, when VCC1 > VCC2. VCC2 = 0V. VCC1 = 0V.
Typical values are at +25°C.
DS1302 Trickle-Charge Timekeeping Chip
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