Chapter 1:StratixIII Device Family Overview
Architecture Features
The design security feature is available when configuring StratixIII FPGAs using the fast passive parallel (FPP) configuration mode with an external host (such as a MAXII device or microprocessor), or when using fast active serial (AS) or passive serial (PS) configuration schemes.
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For more information about the design security feature, refer to the Design Security in StratixIII Devices chapter.
SEU Mitigation
StratixIII devices have built-in error detection circuitry to detect data corruption due to soft errors in the configuration random-access memory (CRAM) cells. This feature allows all CRAM contents to be read and verified continuously during user mode operation to match a configuration-computed CRC value. The enhanced CRC circuit and frame-based configuration architecture allows detection and location of multiple, single, and adjacent bit errors which, in conjunction with a soft circuit supplied as a reference design, allows don’t-care soft errors in the CRAM to be ignored during device operation. This provides a steep decrease in the effective soft error rate, increasing system reliability.
On-chip memory block SEU mitigation is also offered using the ninth bit and a configurable megafunction in the QuartusII software for MLAB and M9K blocks while the M144K memory blocks have built-in error correction code (ECC) circuitry.
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For more information about the dedicated error detection circuitry, refer to the SEU Mitigation in StratixIII Devices chapter.
Programmable Power
StratixIII delivers Programmable Power, the only FPGA with user programmable power options balancing today’s power and performance requirements. StratixIII devices utilize the most advanced power-saving techniques, including a variety of process, circuit, and architecture optimizations and innovations. In addition, user controllable power reduction techniques provide an optimal balance of performance and power reduction specific for each design configured into the StratixIII FPGA. The QuartusII software (starting from version 6.1) automatically optimizes designs to meet the performance goals while simultaneously leveraging the programmable power-saving options available in the StratixIII FPGA without the need for any changes to the design flow.
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For more information about Programmable Power in StratixIII devices, refer to the following documents:
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Programmable Power and Temperature Sensing Diode in StratixIII Devices chapterAN 437: Power Optimization in StratixIII FPGAsStratixIII Programmable Power White Paper
Stratix III Device Handbook, Volume 1
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