基于FPGA的数字电压表设计

CTL => NlwInverterSignal_v1_1_obuf_GTS_TRI_CTL, O => v1(1) );

v1_0_obuf_GTS_TRI_46 : X_TRI port map (

I => v1_0_obuf_GTS_TRI,

CTL => NlwInverterSignal_v1_0_obuf_GTS_TRI_CTL, O => v1(0) );

v2_3_obuf_GTS_TRI_47 : X_TRI port map (

I => v2_3_obuf_GTS_TRI,

CTL => NlwInverterSignal_v2_3_obuf_GTS_TRI_CTL, O => v2(3) );

v2_2_obuf_GTS_TRI_48 : X_TRI port map (

I => v2_2_obuf_GTS_TRI,

CTL => NlwInverterSignal_v2_2_obuf_GTS_TRI_CTL, O => v2(2) );

v2_1_obuf_GTS_TRI_49 : X_TRI port map (

I => v2_1_obuf_GTS_TRI,

CTL => NlwInverterSignal_v2_1_obuf_GTS_TRI_CTL, O => v2(1) );

v2_0_obuf_GTS_TRI_50 : X_TRI port map (

I => v2_0_obuf_GTS_TRI,

CTL => NlwInverterSignal_v2_0_obuf_GTS_TRI_CTL, O => v2(0) );

v3_3_obuf_GTS_TRI_51 : X_TRI port map (

I => v3_3_obuf_GTS_TRI,

CTL => NlwInverterSignal_v3_3_obuf_GTS_TRI_CTL, O => v3(3) );

v3_2_obuf_GTS_TRI_52 : X_TRI port map (

I => v3_2_obuf_GTS_TRI,

CTL => NlwInverterSignal_v3_2_obuf_GTS_TRI_CTL, O => v3(2)

45

);

v3_1_obuf_GTS_TRI_53 : X_TRI port map (

I => v3_1_obuf_GTS_TRI,

CTL => NlwInverterSignal_v3_1_obuf_GTS_TRI_CTL, O => v3(1) );

v3_0_obuf_GTS_TRI_54 : X_TRI port map (

I => v3_0_obuf_GTS_TRI,

CTL => NlwInverterSignal_v3_0_obuf_GTS_TRI_CTL, O => v3(0) );

v4_3_obuf_GTS_TRI_55 : X_TRI port map (

I => v4_3_obuf_GTS_TRI,

CTL => NlwInverterSignal_v4_3_obuf_GTS_TRI_CTL, O => v4(3) );

v4_2_obuf_GTS_TRI_56 : X_TRI port map (

I => v4_2_obuf_GTS_TRI,

CTL => NlwInverterSignal_v4_2_obuf_GTS_TRI_CTL, O => v4(2) );

v4_1_obuf_GTS_TRI_57 : X_TRI port map (

I => v4_1_obuf_GTS_TRI,

CTL => NlwInverterSignal_v4_1_obuf_GTS_TRI_CTL, O => v4(1) );

v4_0_obuf_GTS_TRI_58 : X_TRI port map (

I => v4_0_obuf_GTS_TRI,

CTL => NlwInverterSignal_v4_0_obuf_GTS_TRI_CTL, O => v4(0) );

v5_3_obuf_GTS_TRI_59 : X_TRI port map (

I => v5_3_obuf_GTS_TRI,

CTL => NlwInverterSignal_v5_3_obuf_GTS_TRI_CTL, O => v5(3) );

v5_2_obuf_GTS_TRI_60 : X_TRI

46

port map (

I => v5_2_obuf_GTS_TRI,

CTL => NlwInverterSignal_v5_2_obuf_GTS_TRI_CTL, O => v5(2) );

v5_1_obuf_GTS_TRI_61 : X_TRI port map (

I => v5_1_obuf_GTS_TRI,

CTL => NlwInverterSignal_v5_1_obuf_GTS_TRI_CTL, O => v5(1) );

v5_0_obuf_GTS_TRI_62 : X_TRI port map (

I => v5_0_obuf_GTS_TRI,

CTL => NlwInverterSignal_v5_0_obuf_GTS_TRI_CTL, O => v5(0) );

NlwBlock_ym_GND : X_ZERO port map ( O => GND );

NlwInverterBlock_v1_3_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v1_3_obuf_GTS_TRI_CTL );

NlwInverterBlock_v1_2_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v1_2_obuf_GTS_TRI_CTL );

NlwInverterBlock_v1_1_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v1_1_obuf_GTS_TRI_CTL );

NlwInverterBlock_v1_0_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v1_0_obuf_GTS_TRI_CTL );

NlwInverterBlock_v2_3_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

47

O => NlwInverterSignal_v2_3_obuf_GTS_TRI_CTL );

NlwInverterBlock_v2_2_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v2_2_obuf_GTS_TRI_CTL );

NlwInverterBlock_v2_1_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v2_1_obuf_GTS_TRI_CTL );

NlwInverterBlock_v2_0_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v2_0_obuf_GTS_TRI_CTL );

NlwInverterBlock_v3_3_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v3_3_obuf_GTS_TRI_CTL );

NlwInverterBlock_v3_2_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v3_2_obuf_GTS_TRI_CTL );

NlwInverterBlock_v3_1_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v3_1_obuf_GTS_TRI_CTL );

NlwInverterBlock_v3_0_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v3_0_obuf_GTS_TRI_CTL );

NlwInverterBlock_v4_3_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v4_3_obuf_GTS_TRI_CTL );

NlwInverterBlock_v4_2_obuf_GTS_TRI_CTL : X_INV port map (

48