基于FPGA的数字电压表设计

port map ( I => v55(2),

O => v5_2_obuf_GTS_TRI );

v55_madd_n0000_inst_sum_3 : X_XOR2 port map (

I0 => v55_madd_n0000_inst_cy_2, I1 => v55_3_rt, O => v55_n0000(3) );

v55_madd_n0000_inst_cy_1_5 : X_MUX2 port map (

IA => v2_0_obuf,

IB => v55_madd_n0000_inst_cy_0, SEL => v55_1_rt,

O => v55_madd_n0000_inst_cy_1 );

v55_madd_n0000_inst_sum_1 : X_XOR2 port map (

I0 => v55_madd_n0000_inst_cy_0, I1 => v55_1_rt, O => v55_n0000(1) );

v33_madd_n0000_inst_sum_3 : X_XOR2 port map (

I0 => v33_madd_n0000_inst_cy_2, I1 => v33_3_rt, O => v33_n0000(3) );

v44_madd_n0000_inst_cy_2_6 : X_MUX2 port map (

IA => v2_0_obuf,

IB => v44_madd_n0000_inst_cy_1, SEL => v44_2_rt,

O => v44_madd_n0000_inst_cy_2 );

v44_madd_n0000_inst_sum_2 : X_XOR2 port map (

I0 => v44_madd_n0000_inst_cy_1, I1 => v44_2_rt, O => v44_n0000(2) );

v44_madd_n0000_inst_cy_0_7 : X_MUX2 port map (

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IA => n290, IB => v2_0_obuf,

SEL => v44_madd_n0000_inst_lut2_0, O => v44_madd_n0000_inst_cy_0 );

v5_1_obuf : X_BUF port map ( I => v55(1),

O => v5_1_obuf_GTS_TRI );

v44_madd_n0000_inst_sum_3 : X_XOR2 port map (

I0 => v44_madd_n0000_inst_cy_2, I1 => v44_3_rt, O => v44_n0000(3) );

v44_madd_n0000_inst_cy_1_8 : X_MUX2 port map (

IA => v2_0_obuf,

IB => v44_madd_n0000_inst_cy_0, SEL => v44_1_rt,

O => v44_madd_n0000_inst_cy_1 );

v44_madd_n0000_inst_sum_1 : X_XOR2 port map (

I0 => v44_madd_n0000_inst_cy_0, I1 => v44_1_rt, O => v44_n0000(1) );

Q_n000926 : X_LUT4 generic map( INIT => X\ )

port map (

ADR0 => q_2_ibuf, ADR1 => q_1_ibuf, ADR2 => q_3_ibuf, ADR3 => q_0_ibuf, O => choice81 );

Q_n001019_sw0 : X_LUT4 generic map( INIT => X\ )

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port map (

ADR0 => q_6_ibuf, ADR1 => q_1_ibuf, ADR2 => q_2_ibuf, ADR3 => q_3_ibuf, O => n1239 );

Q_n00105 : X_LUT2 generic map( INIT => X\ )

port map (

ADR0 => q_4_ibuf, ADR1 => q_5_ibuf, O => choice66 );

mcompar_n0011_agb8 : X_LUT2 generic map( INIT => X\ )

port map (

ADR0 => q_7_ibuf, ADR1 => choice60, O => n1063 );

mcompar_n0011_agb6 : X_LUT4 generic map( INIT => X\ )

port map (

ADR0 => q_4_ibuf, ADR1 => q_2_ibuf, ADR2 => q_3_ibuf, ADR3 => choice59, O => choice60 );

mcompar_n0011_agb3 : X_LUT2 generic map( INIT => X\ )

port map (

ADR0 => q_5_ibuf, ADR1 => q_6_ibuf, O => choice59

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);

reset_ibuf_9 : X_BUF port map ( I => reset, O => reset_ibuf );

q_7_ibuf_10 : X_BUF port map ( I => q(7), O => q_7_ibuf );

q_6_ibuf_11 : X_BUF port map ( I => q(6), O => q_6_ibuf );

q_5_ibuf_12 : X_BUF port map ( I => q(5), O => q_5_ibuf );

q_4_ibuf_13 : X_BUF port map ( I => q(4), O => q_4_ibuf );

q_3_ibuf_14 : X_BUF port map ( I => q(3), O => q_3_ibuf );

q_2_ibuf_15 : X_BUF port map ( I => q(2), O => q_2_ibuf );

q_1_ibuf_16 : X_BUF port map ( I => q(1), O => q_1_ibuf );

q_0_ibuf_17 : X_BUF port map ( I => q(0),

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