OCT calibration is automatically performed at power-up for OCT-enabled I/Os. Table1–13 lists OCT variation with temperature and voltage after power-up
calibration. Use Table1–13 to determine the OCT variation after power-up calibration and Equation1–1 to determine the OCT variation without re-calibration.Equation1–1.OCT Variation Without Re-Calibration(1), (2), (3), (4), (5), (6)
dRdR
-??V??ROCT=RSCAL?1+?------??T???------??dTdV
Notes to Equation1–1:
(1)The ROCT value calculated from Equation1–1 shows the range of OCT resistance with the variation of temperature
and VCCIO.(2)RSCAL is the OCT resistance value at power-up.
(3)?T is the variation of temperature with respect to the temperature at power-up.(4)?V is the variation of voltage with respect to the VCCIO at power-up.(5)dR/dT is the percentage change of RSCAL with temperature.(6)dR/dV is the percentage change of RSCAL with voltage.
Table1–13 lists the OCT variation after the power-up calibration.Table1–13.OCT Variation after Power-Up Calibration (1)
Symbol
Description
VCCIO (V)3.0
dR/dV
OCT variation with voltage without re-calibration
2.51.81.51.23.0
dR/dT
OCT variation with temperature without re-calibration
2.51.81.51.2
Note to Table1–13:
(1)Valid for VCCIO range of ±5% and temperature range of 0° to 85°C.
Typical0.02970.03440.04990.07440.12410.1890.2080.2660.2730.317
Unit
%/mV
%/°C
Pin Capacitance
Table1–14 lists the Stratix IV device family pin capacitance.
Table1–14.Pin Capacitance for Stratix IV Devices (Part 1 of 2)
SymbolCIOTBCIOLRCCLKTBCCLKLR
Description
Input capacitance on the top and bottom I/O pinsInput capacitance on the left and right I/O pins
Input capacitance on the top and bottom non-dedicated clock input pinsInput capacitance on the left and right non-dedicated clock input pins
Value4444
UnitpFpFpFpF
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table1–30.Transceiver Block Jitter Specifications for Stratix IV GX Devices(1), (2) (Part 9 of 9)
–2 CommercialSpeed GradeMinTyp
Jitter Frequency = 21.8 KHz
Sinusoidal Jitter
tolerance at 3072Mbps
Pattern = CJPATJitter Frequency = 1843.2MHz to 20MHzPattern = CJPAT
Notes to Table1–30:
Symbol/Description
Conditions
–3 Commercial/Industrial
and –2× Commercial
Speed GradeMin
Typ>8.5
Max
–3 Military(3) and–4 Commercial/Industrial Speed
GradeMinTyp
>8.5
Max
Unit
Max
>8.5UI
>0.1>0.1>0.1UI
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV DevicesSwitching Characteristics
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table1–31.Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 2 of 2)Symbol/Description
Conditions
Jitter Frequency = 40KHzPattern = PRBS-31 Equalization = Disabled
Sinusoidal Jitter tolerance
BER = 1E-12
Jitter Frequency ?4MHzPattern = PRBS-31Equalization = DisabledBER = 1E-12
>0.05
>0.05
—
UI
>5
>5
—
UI
–1 Industrial Speed –2 Industrial Speed –3 Industrial Speed
GradeGradeGradeMin
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1:DC and Switching Characteristics for Stratix IV DevicesSwitching Characteristics
Table1–37.Configuration Mode Specifications for Stratix IV Devices
Programming Mode
Remote update only in fast AS mode
Note to Table1–37:
(1)This denotes the maximum frequency supported in the FPP configuration scheme. The frequency supported for
each device may vary depending on device density. For more information, refer to the Configuration, DesignSecurity, and Remote System Upgrades in Stratix IV Devices chapter.
DCLK FMAX
Min4.3
Typ5.3
Max10
UnitMHz
Table1–38 lists the JTAG timing parameters and values for Stratix IV devices. Table1–38.JTAG Timing Parameters and Values for Stratix IV Devices
SymboltJCPtJCHtJCLtJPSU (TDI)tJPSU (TMS)tJPHtJPCOtJPZXtJPXZ
Description
TCK clock periodTCK clock high timeTCK clock low timeTDI JTAG port setup timeTMS JTAG port setup timeJTAG port hold timeJTAG port clock to output
JTAG port high impedance to valid outputJTAG port valid output to high impedance
Min301414135———
Max——————11 (1)14 (1)14 (1)
Unitnsnsnsnsnsnsnsnsns
Note to Table1–38:
(1)A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
Temperature Sensing Diode Specifications
Table1–39 lists the specifications for the Stratix IV temperature sensing diode.Table1–39.External Temperature Sensing Diode Specifications for StratixIV Devices
Description
Ibias, diode source currentVbias, voltage across diodeSeries resistanceDiode ideality factor
Min80.3—1.026
Typ———1.028
Max5000.9< 51.030
Unit?AV?—
Table1–40 lists the specifications for the Stratix IV internal temperature sensing diode.
Table1–40.Internal Temperature Sensing Diode Specifications for StratixIV DevicesTemperature
Accuracy
Range–40 to 100°C
±8°C
Offset Calibrated
Option
No
Sampling RateFrequency: 500kHz, 1MHz
Conversion Time<100ms
Resolution8bits
Minimum Resolution with No Missing Codes
8bits
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
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