(有代码)基于libero的数字逻辑设计仿真及验证实验(4-8)

);

Endmodule

//74HC283代码

//HC283.v

module HC283(A3,A2,A1,A0,B3,B2,B1,B0,Sigma3,Sigma2,Sigma1,Sigma0,C0,C4); input A3,A2,A1,A0,B3,B2,B1,B0; input C0;

output Sigma3,Sigma2,Sigma1,Sigma0; output C4; reg C4;

reg[3:0]Sigma;

wire[3:0]DataA,DataB; assign DataA[0]=A0; assign DataA[1]=A1; assign DataA[2]=A2; assign DataA[3]=A3; assign DataB[0]=B0; assign DataB[1]=B1; assign DataB[2]=B2; assign DataB[3]=B3;

always @(DataA or DataB or C0) begin

{C4,Sigma}=DataA+DataB+C0; end

assign Sigma0= Sigma[0]; assign Sigma1= Sigma[1]; assign Sigma2= Sigma[2]; assign Sigma3= Sigma[3]; endmodule

//74HC283测试平台代码 // test283.v

`timescale 1ns/10ps module test283;

reg A3,A2,A1,A0,B3,B2,B1,B0; reg C0;

wire Sigma3,Sigma2,Sigma1,Sigma0; wire C4; initial begin A3=0; repeat(20)

#20 A3=$random; end

initial begin A2=0; repeat(20)

#20 A2=$random; end initial begin A1=0; repeat(20)

#20 A1=$random; end initial begin A0=0; repeat(20)

#20 A0=$random; end initial begin B3=0; repeat(20)

#20 B3=$random; end initial begin B2=0; repeat(20)

#20 B2=$random; end initial begin B1=0; repeat(20)

#20 B1=$random; end initial begin B0=0; repeat(20)

#20 B0=$random; end initial begin

C0=0; repeat(20)

#20 C0=$random; end

HC283 u283 (

.A3 (A3), .A2 (A2), .A1 (A1), .A0 (A0), .B3 (B3), .B2 (B2), .B1 (B1), .B0 (B0),

.Sigma3 (Sigma3), .Sigma2 (Sigma2), .Sigma1 (Sigma1), .Sigma0 (Sigma0), .C0 (C0), .C4 (C4) );

Endmodule

//74HC4511代码

//HC4511.v

module HC4511(A,Seg,LT_N,BI_N,LE); input LT_N,BI_N,LE; input[3:0]A; output[7:0]Seg; reg[7:0]SM_8S; assign Seg=SM_8S;

always@(A or LT_N or BI_N or LE) begin

if(!LT_N)SM_8S=8'b11111111; else if(!BI_N)SM_8S=8'b00000000; else if(LE)SM_8S=SM_8S; else case(A)

4'd0:SM_8S=8'b00111111; 4'd1:SM_8S=8'b00000110; 4'd2:SM_8S=8'b01011011; 4'd3:SM_8S=8'b01001111; 4'd4:SM_8S=8'b01100110;

4'd5:SM_8S=8'b01101101; 4'd6:SM_8S=8'b01111101; 4'd7:SM_8S=8'b00000111; 4'd8:SM_8S=8'b01111111; 4'd9:SM_8S=8'b01101111; 4'd10:SM_8S=8'b01110111; 4'd11:SM_8S=8'b01111100; 4'd12:SM_8S=8'b00111001; 4'd13:SM_8S=8'b01011110; 4'd14:SM_8S=8'b01111001; 4'd15:SM_8S=8'b01110001; default:; endcase end

endmodule

//74HC4511测试平台代码 // test4511.v

`timescale 1ns/1ps module test4511; reg [3:0]pA;

reg pLT_N,pBI_N,pLE; wire [7:0] pSeg;

HC4511 u4511(pA,pSeg,pLT_N,pBI_N,pLE); initial begin

pA=0;pLT_N=0;pBI_N=0;pLE=0; #10 pLT_N=0;

#10 pLT_N=1;pBI_N=0;

#10 pLE=0;pLT_N=1;pBI_N=1;pA=4'd0; #10 pA=4'd0; #10 pA=4'd1; #10 pA=4'd2; #10 pA=4'd3; #10 pA=4'd4; #10 pA=4'd5; #10 pA=4'd6; #10 pA=4'd7; #10 pA=4'd8; #10 pA=4'd9; #10 pA=4'd10; #10 pA=4'd11; #10 pA=4'd12; #10 pA=4'd13; #10 pA=4'd14;