Table1–35.StratixIII Memory Output Clock Jitter Specification (Note1), (2),(3)
C2
Clock NetworkRegionalRegionalRegionalGlobalGlobalGlobal
VCCL = 1.1V
SymboltJIT(per)tJIT(cc)tJIT(duty)tJIT(per)tJIT(cc)
Min–70–150–80–105–225
Max7015080105225120
C3, I3VCCL = 1.1VMin–85–170–90–128–255–135
Max8517090128255135
C4, I4VCCL = 1.1VMin Max–100–190–100–150–285–150
100190100150285150
C4L, I4L
VCCL = 1.1VMin Max–100–190–100–150–285–150
100190100150285150
VCCL = 0.9VMin Max–120–230–140–180–340–180
120230140180340180
pspspspspspsUnit
ParameterClock period jitterCycle-to-cycle period jitterDuty cycle jitterClock period jitterCycle-to-cycle period jitterDuty cycle jitter
Notes to Table1–35:
tJIT(duty)–120
(1)The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 standard.
(2)The clock jitter specification applies to memory output clock pins generated using differential signal-splitter & DDIO circuits clocked by a PLL output routed on
a regional or global clock network as specified. Use of regional clock networks are recommended whenever possible.(3)The memory output clock jitter stated in the table is applicable when an input jitter of 30ps is applied.
OCT Calibration Block Specifications
Table1–36 shows the on-chip termination calibration block specifications for StratixIII devices.
Table1–36.On-Chip Termination Calibration Block Specification
SymbolOCTUSRCLKtOCTCALtOCTSHIFTtRS_RT
Description
Clock required by OCT calibration blocks Number of OCTUSRCLK clock cycles required for OCT Rs and Rt calibration
Number of OCTUSRCLK clock cycles required for OCT code to shift out per OCT calibration blockTime required to dynamically switch from Rs to Rt
Min————
Typical—1000282.5
Max20———
UnitMHzcyclescyclesns
DCD Specifications
Table1–37 lists the worst case duty cycle distortion for StratixIII devices. Detailed information on duty cycle distortion will be published after characterization. Table1–37.Duty Cycle Distortion on StratixIII I/O Pins(Note1)
Symbol
Output Duty Cycle
Note to Table1–37:
(1)DCD specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated and general
purpose I/O pins.
C2Min45
Max55
Min45
C3Max55
Min45
C4Max55
Unit%
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Figure1–5.Output Register Clock to Output Timing Diagram
DatainClockClock pad to output Register delayOutput Register micro tCOOutput Register to output pin delayOutputSimulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the QuartusII software and the timing model in the device handbook.
1.Simulate the output driver of choice into the generalized test setup, using values
from Table1–39.2.Record the time to VMEAS at the far end of the PCB trace.
3.Simulate the output driver of choice into the actual PCB trace and load, using the
appropriate IBIS model or capacitance value to represent the load.4.Record the time to VMEAS at the far end of the PCB trace.
5.Compare the results of steps 2 and 4. The increase or decrease in delay should be
added to or subtracted from the I/O Standard Output Adder delays to yield theactual worst-case propagation delay (clock-to-output) of the PCB trace.The QuartusII software reports the timing with the conditions shown in Table1–39 using the above equation. Figure1–6 shows the model of the circuit that is represented by the output timing of the QuartusII software.
Figure1–6.Output Delay Timing Reporting Setup Modeled by QuartusII Software for Single-Ended Outputs and Dedicated Differential Outputs (Note1)
VCCIOVTTOutputpRDRTOutputBufferOutputRSCLGNDVMEASOutputnGNDNote to Figure1–6:
(1)Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay
need to be accounted for with IBIS model simulations.
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Figure1–7 and Figure1–8 show the model of the circuit that is represented by the output timing of the QuartusII software for differential outputs with single and multiple external resistors.
Figure1–7.Output Delay Timing Reporting Setup Modeled by QuartusII Software for Differential Outputs with Single External Resistor
Non-DedicatedDifferential Outputs VMEASRPVMEASRD
Figure1–8.Output Delay Timing Reporting Setup modeled by QuartusII Software for Differential Outputs with Three External Resistor
Non-DedicatedDifferential Outputs VMEASRSRPRDVMEASRSTable1–39.Output Timing Measurement Methodology for Output Pins(Part 1 of 3)
I/O Standard
RS
3.3-V LVTTL3.3-V LVCMOS3.0-V LVTTL3.0-V LVCMOS2.5-V1.8-V1.5-V1.2-VPCIPCI-X
SSTL-2 CLASSISSTL-2 CLASSIISSTL-18 CLASSISSTL-18 CLASSIISSTL-15 CLASSISSTL-15 CLASSII1.8-V HSTL CLASSI
——————————252525252525—
RD—————————————————
RT——————————50255025502550
Loading and TerminationsRP—————————————————
VCCIO3.1353.1352.852.852.3751.711.4251.142.852.852.3252.3251.661.661.3751.3751.66
VCCPD3.1353.1352.852.852.3752.3752.3752.3752.852.852.3252.3252.3252.3252.3252.3252.325
VCC1.051.051.051.051.051.051.051.051.051.051.021.021.021.021.021.021.02
VTT——————————1.251.250.900.900.750.750.90
CL (pF)0000000010100000000
Measurement
PointVMEAS (v)1.56751.56751.4251.4251.18750.8550.71250.571.4251.4251.16251.16250.830.830.68750.68750.83
Stratix III Device Handbook, Volume 2
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