Spartan-3 FPGA Family: Functional Description
The product of w and n yields the total block RAM capacity. Equation1 and Equation2 show that as the data bus width increases, the number of address lines along with the number of addressable memory locations decreases. Using the permissible DI/DO bus widths as inputs to these equations provides the bus width and memory capacity measures shown in Table14.
Table 14:Port Aspect Ratios for Port A or B
DI/DO Bus Width(w – p Bits)
12481632
DIP/DOP Bus Width (p Bits)
000124
Total Data Path Width (w Bits)
12491836
ADDR Bus Width
(r Bits)
14131211109
No. of Addressable Block RAM Locations (n)Capacity (Bits)
16,3848,1924,0962,0481,024512
16,38416,38416,38418,43218,43218,432
Block RAM Data Operations
Writing data to and accessing data from the block RAM are synchronous operations that take place independently on each
of the two ports.
The waveforms for the write operation are shown in the top half of the Figure15, Figure16, and Figure17. When the WE and EN signals enable the active edge of CLK, data at the DI input bus is written to the block RAM location addressed by the ADDR lines.
There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by the ADDR lines passes through a transparent output latch to the DO outputs. The timing for basic data access is shown in the portions of Figure15, Figure16, and Figure17 during which WE is Low.
X-Ref Target - Figure 15CLKWEDIADDRDOXXXX11112222XXXXaabbccdd0000MEM(aa)11112222MEM(dd)ENDISABLEDREADWRITEMEM(bb)=1111WRITEMEM(cc)=2222READDS099-2_14_091410Figure 15:Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Data can also be accessed on the DO outputs when asserting the WE input. This is accomplished using two different attributes:
Choosing the WRITE_FIRST attribute, data is written to the addressed memory location on an enabled active CLK edge and is also passed to the DO outputs. WRITE_FIRST timing is shown in the portion of Figure15 during which WE is High.Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that location is overwritten with new data from the DI inputs on an enabled active CLK edge. READ_FIRST timing is shown in the portion of Figure16 during which WE is High.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 22Phase:0o90180270ooo0o90180270ooo0oInput Signal (40% Duty Cycle)tCLKINOutput Signal - Duty Cycle is Always CorrectedCLK2XCLK2X180(1)CLKDVOutput Signal - Attribute Corrects Duty CycleDUTY_CYCLE_CORRECTION = FALSECLK0CLK90CLK180CLK270DUTY_CYCLE_CORRECTION = TRUECLK0CLK90CLK180CLK270DS099-2_10_051907Figure 22:Characteristics of the DLL Clock Outputs
Digital Frequency Synthesizer (DFS)
The DFS component generates clock signals the frequency of which is a product of the clock frequency at the CLKIN input and a ratio of two user-determined integers. Because of the wide range of possible output frequencies such a ratio permits, the DFS feature provides still further flexibility than the DLL’s basic synthesis options as described in the preceding section. The DFS component’s two dedicated outputs, CLKFX and CLKFX180, are defined in Table19.
The signal at the CLKFX180 output is essentially an inversion of the CLKFX signal. These two outputs always exhibit a 50% duty cycle. This is true even when the CLKIN signal does not. These DFS clock outputs are driven at the same time as the DLL’s seven clock outputs.
The numerator of the ratio is the integer value assigned to the attribute CLKFX_MULTIPLY and the denominator is the integer value assigned to the attribute CLKFX_DIVIDE. These attributes are described in Table18.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
Interconnect
Interconnect (or routing) passes signals among the various functional elements of Spartan-3 devices. There are four kinds of interconnect: Long lines, Hex lines, Double lines, and Direct lines.
Long lines connect to one out of every six CLBs (see section [a] of Figure25). Because of their low capacitance, these lines are well-suited for carrying high-frequency signals with minimal loading effects (e.g. skew). If all eight Global Clock Inputs are already committed and there remain additional clock signals to be assigned, Long lines serve as a good alternative.Hex lines connect one out of every three CLBs (see section [b] of Figure25). These lines fall between Long lines and Double lines in terms of capability: Hex lines approach the high-frequency characteristics of Long lines at the same time, offering greater connectivity.
Double lines connect to every other CLB (see section [c] of Figure25). Compared to the types of lines already discussed, Double lines provide a higher degree of flexibility when making connections.
Direct lines afford any CLB direct access to neighboring CLBs (see section [d] of Figure25). These lines are most often used to conduct a signal from a \line accessing a \
For more details, refer to the “Using Interconnect” chapter in UG331.
X-Ref Target - Figure 25CLBCLBCLBCLBCLBCLBCLBCLBCLBCLB????????????6666DS099-2_19_040103(a)Long Lines
8CLBCLBCLBCLBCLBCLB???6CLBDS099-2_20_040103(b)Hex Lines
CLB2CLBCLBCLBCLBDS099-2_21_040103CLBCLBCLBCLB(c)Double LinesCLBCLBCLBDS099-2_22_040103(d)Direct Lines
Figure 25:Types of Interconnect
DS099 (v3.1) June 27, 2013
Product Specification
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