(完整版)FPGA课程设计基于FPGA器件设计与实现毕业论文

目录

摘 要 ..................................................................

ABSTRACT ................................................................

引言 ....................................................................

1项目构成的基本原理 .....................................................

1.1 、UART简介 ........................................................

1.2、UART的基本特点 ...................................................

2项目实现的基本原则 .....................................................

2.1、FPGA UART系统组成如图2所示： .....................................

2.2、波特率发生器 ......................................................

2.3、UART接收器 .......................................................

2.4、UART发送器 .......................................................

2.5芯片的选择 .........................................................

3程序设计 ...............................................................

3.1顶层程序 ...........................................................

3.2 UART发送器程序 ....................................................

3.3 UART接收器程序 ....................................................

3.4整体电路图 .........................................................

4仿真 ...................................................................

4.1顶层仿真 ...........................................................

4.2波特率发生器仿真 ...................................................

4.3UART发送器仿真 .....................................................

4.4 UART接收器仿真 ....................................................

5总结 ...................................................................

6参考文献 ...............................................................

摘 要

基于FPGA设计和实现UART，可以用片上很少的逻辑单元实现UART的基本功能。与传统设计相比，能有效减少系统的PCB面积，降低系统的功耗，提高设计的稳定性和可靠性，并可方便地进行系统升级和移植。

采用有限状态机模型形式化描述了UART的功能,在此基础上用硬件描述语言VHDL编程实现了UART，并使用QuartusⅡ软件中的嵌入式逻辑分析仪SignalTap对数据传输进行了检测,验证了设计的正确性。 本设计具有较大的灵活性，通过调整波特率发生器的分频参数，就可以使其工作在不同的频率。采用16倍波特率的采样时钟，可以实时有效探测数据的起始位，并可对数据位进行“对准”中央采样，保证了所采样数据的正确性。该模块可以作为一个完整的IP核移植进各种FPGA中，在实际应用时可嵌入到其他系统中，很容易实现和远端上位机的异步通信。

关键字: FPGA；UART；有限状态机；SignalTap

Abstract

Design and implementation based on FPGA UART, can be used on a few logical unit realizes the basic function of UART. Compared with the traditional design, can effectively reduce the PCB area system, reduce the power consumption of the system, and improve the design of the stability and reliability, and easy system upgrades and migration.

The functions of UART are described formally by using the finite state machinemodel, by the way, UART is realized on the basis of VHDL . Moreover, the data transmission is detected with SignalTap which is an embedded logic analyzer in QuartusⅡ. The result proves the validity of the design.

This design baud rate generator parameters, you can make it work on a different frequency. Using 16 times the baud rate of the sampling clock, can effectively detect real-time data of the start bit, and to \central sampling of data bits, ensures the correctness of the sampled data. The module can be used as a complete IP nuclear transplantation into various kinds of FPGA, in the actual application can be embedded into other systems, is easy to implement and the remote PC asynchronous communication.

Key word: FPGA；UART；finite state machine；SignalTap