(完整版)FPGA课程设计基于FPGA器件设计与实现毕业论文

3程序设计

3.1顶层程序

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is

Port (clk32mhz,reset,rxd,xmit_cmd_p_in:in std_logic; --总的输入输出信号的定义

rec_ready,txd_out,txd_done_out:out std_logic;

txdbuf_in:in std_logic_vector(7 downto 0); --待发送数据输入

rec_buf:out std_logic_vector(7 downto 0)); --接收数据缓冲

end top;

architecture Behavioral of top is component reciever

Port (bclkr,resetr,rxdr:in std_logic;

r_ready:out std_logic;

rbuf:out std_logic_vector(7 downto 0));

end component; component transfer

Port (bclkt,resett,xmit_cmd_p:in std_logic;

txdbuf:in std_logic_vector(7 downto 0);

txd:out std_logic; txd_done:out std_logic);

end component; component baud

Port (clk,resetb:in std_logic;

bclk:out std_logic);

end component; signal b:std_logic; begin u00001:baud --顶层映射

u2:reciever

map(bclkr=>b,resetr=>reset,rxdr=>rxd,r_ready=>rec_ready,

rbuf=>rec_buf); u3:transfer

map(bclkt=>b,resett=>reset,xmit_cmd_p=>xmit_cmd_p_in,

txdbuf=>txdbuf_in,txd=>txd_out,txd_done=>txd_done_out);

end Behavioral;

port port

port

map(clk=>clk32mhz,resetb=>reset,bclk=>b);

3.2波特率发生器程序

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity baud is

Port (clk,resetb:in std_logic;

bclk:out std_logic);

end baud;

architecture Behavioral of baud is begin

process(clk,resetb) variable cnt:integer; begin

if resetb='1' then cnt:=0; bclk<='0'; 复位

elsif rising_edge(clk) then

if cnt>=208 then cnt:=0; bclk<='1'; 设置分频系数

else cnt:=cnt+1; bclk<='0';

end if;

end if; end process; end Behavioral;

3.2 UART发送器程序

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

----

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity transfer is

generic(framlent:integer:=8);

Port (bclkt,resett,xmit_cmd_p:in std_logic; --定义输入输出信号

txdbuf:in std_logic_vector(7 downto 0):=\ txd:out std_logic;

txd_done:out std_logic);

end transfer;

architecture Behavioral of transfer is

type states is (x_idle,x_start,x_wait,x_shift,x_stop); 个子状态

signal state:states:=x_idle; signal tcnt:integer:=0; begin

process(bclkt,resett,xmit_cmd_p,txdbuf) 时序、组合进程

variable xcnt16:std_logic_vector(4 downto 0):=\ 中间变量

variable xbitcnt:integer:=0; variable txds:std_logic; begin

if resett='1' then state<=x_idle; txd_done<='0'; txds:='1'; elsif rising_edge(bclkt) then

--定义--主控--定义--复位