case state is
when x_idle=> --状态1，等
待数据帧发送命令
if xmit_cmd_p='1' then state<=x_start; txd_done<='0';
else state<=x_idle; end if;
when x_start=> --状态2，发送信号至起始位
if xcnt16>=\else xcnt16:=xcnt16+1; txds:='0'; state<=x_start; end if;
when x_wait=> --状态3，等待状态
if xcnt16>=\
if xbitcnt=framlent then state<=x_stop; xbitcnt:=0;
else state<=x_shift; end if;
xcnt16:=\
else xcnt16:=xcnt16+1; state<=x_wait;
end if;
x_shift=>txds:=txdbuf(xbitcnt);
xbitcnt:=xbitcnt+1;
when state<=x_wait;
--
状态4，将待发数据进行并串转换
when x_stop=> --状态5，停止位发送状态 if xcnt16>=\
if xmit_cmd_p='0' then state<=x_idle;
xcnt16:=\
else xcnt16:=xcnt16; state<=x_stop; end if; txd_done<='1';
else xcnt16:=xcnt16+1; txds:='1'; state<=x_stop;
end if;
when others=>state<=x_idle;
end case;
end if; txd<=txds; end process; end Behavioral;
3.3 UART接收器程序
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity reciever is
generic(framlenr:integer:=8);
Port (bclkr,resetr,rxdr:in std_logic; 义输入输出信号
r_ready:out std_logic;
rbuf:out std_logic_vector(7 downto 0));
end reciever;
--定
architecture Behavioral of reciever is
type states is (r_start,r_center,r_wait,r_sample,r_stop); --定义各子状态
signal state:states:=r_start; signal rxd_sync:std_logic; begin
pro1:process(rxdr) begin
if rxdr='0' then rxd_sync<='0'; else rxd_sync<='1'; end if; end process;
pro2:process(bclkr,resetr,rxd_sync) 控时序、组合进程
variable count:std_logic_vector(3 downto 0); 定义中间变量
variable rcnt:integer:=0;
variable rbufs:std_logic_vector(7 downto 0); begin if resetr='1'
then
state<=r_start;
--复位
elsif rising_edge(bclkr) then case state is
when r_start=> 态1，等待起始位
--主 --count:=\ --状
if rxd_sync='0' then state<=r_center; r_ready<='0'; rcnt:=0;
else state<=r_start; r_ready<='0'; end if;
when r_center=> --状态2，求出每位的中点
if rxd_sync='0' then
if count=\
else count:=count+1; state<=r_center; end if;
else state<=r_start;
end if;
when r_wait=> --状态3，等待状态
if count>=\
if rcnt=framlenr then state<=r_stop;
else state<=r_sample; end if;
count:=\
else count:=count+1; state<=r_wait;
end if;
when r_sample=>rbufs(rcnt):=rxd_sync; rcnt:=rcnt+1;state<=r_wait; --状态4，数据位采样检测
when r_stop=>r_ready<='1'; rbuf<=rbufs; state<=r_start;
--状态4，输出帧
相关推荐：
loading