KT0806L_V1.4

KT0806L

CURRENT ADDRESS READ: The internal data register address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained.

Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the KT0806L, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 4).

CURRENT REGISTER READ PROCEDURE S 0 1 1 0 1 1 0R A AP 7 bit address data Acknowledge STOP condition START condition READ command NO Acknowledge

Figure 4: Serial Interface Protocol

Note: The serial controller supports slave mode only. Any register can be addressed randomly.

The address of the slave in the first 7 bits and the 8th bit tells whether the master is receiving data from the slave or transmitting data to the slave. The I2C write address is 0x6C and the read address is 0x6D.

4.2 Slave Mode Protocol

With reference to the clocking scheme shown in Figure 5, the serial interface operates in the following manner:

Figure 5: Serial Interface Slave Mode Protocol

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 6). Data changes during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 7).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the KT0806L in a standby power mode (see Figure 7).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the KT0806L in 8-bit words. The KT0806L sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle (see Figure 8).

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KT0806L

Figure 6: Clock and Data Transitions

Figure 7: Start and Stop Definition

Figure 8: Acknowledge

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5 Register Bank

KT0806L

The register bank stores channel frequency codes, calibration parameters, operation status, mode and power controls, which can be accessed by the internal digital controller, state machines and external micro controllers through the serial interface.

All registers are 8 bits wide. Control logics are active high unless specifically noted.

Register 7 6 5 4 3 2 1 0

0x00 CHSEL[8:1] 0x01 RFGAIN[1:0] PGA[2:0] CHSEL[11:9] 0x02 CHSEL[0] RFGAIN[3]- - MUTE PLTADJ - PHTCNST0x04 ALC_EN MONO PGA_LSB[1:0] - - 0x0B Standby - PDPA - - AUTO_PA- -

DN

0x0C ALC_DECAY_TIME[3:0] ALC_ATTACK_TIME[3:0] 0x0E - - - - - - PA_BIAS - 0x0F - - - PW_OK - SLNCID - - 0x10 - - - - - - PGAMOD0x12 SLNCDIS SLNCTHL[2:0] SLNCTHH[2:0] SW_MOD0x13 RFGAIN[2] - - - - PA_CTRL - - 0x14 SLNCTIME[2:0] SLNCCNTHIGH[2:0] - SLNCTIM

E[3]

0x15 ALCCMPGAIN[2:0] 0x16 - - - SLNCCNTLOW[2:0] 0x17 - FDEV AU_ENHA XTAL_SE

NCE L

0x1E DCLK XTALD REF_CLK[3:0]

0x26 ALCHOLD[2:0] ALCHIGHTH[2:0] 0x27 ALCLOWTH[3:0]

Note 1: ONLY read/write the defined registers. Note 2: Shaded registers are used in KT0806.

5.1 Register 0x00 (Address: 0x00, Default value: 0x5C)

Bit 7 6 5 4 3 2 1 0

KT0806L CHSEL[8:1]

Please note that the default channel of KT0806L is 86MHz instead of 89.7MHz in KT0806

CHSEL[11:0] = Dec2Bin (Target frequency in MHz x 20),

where CHSEL[11:0] = Reg0x1[2:0]:Reg0x0[7:0]:Reg0x2[7]

5.2 Register 0x01 (Address: 0x01, Default value: 0xC3)

Bit 7 6

KT0806L RFGAIN[1:0] 5

4 3 PGA[2:0]

2

1 0 CHSEL[11:9]

Bits 7:6

Type RW

Default 11

Label

RFGAIN[1:0]

Description

Transmission Range Adjustment with RFGAIN[3] in Reg 0x02[6] and RFGAIN[2] in Reg 0x13[7] (See Table 4 below)

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Bits Type Default 5:3 RW 000

Label PGA[2:0]

KT0806L

Description

PGA Gain Control (see PGA_LSB description, Reg 0x04)

111: 12dB 110: 8dB 101: 4dB 100: 0dB 000: 0dB 001: -4dB 010: -8dB 011: -12dB

FM Channel Selection[11:9]

2:0 RW 011 CHSEL[11:9]

Table 4: Transmission power setting

RFGAIN[3:0] RFOUT

0000 95.5 dBuV 0001 96.5 dBuV

0010 97.5 dBuV 0011 98.2 dBuV 0100 98.9 dBuV 0101 100 dBuV

0110 101.5 dBuV 0111 102.8 dBuV 1000 105.1 dBuV (107.2dBuV PA_BIAS=1) 1001 105.6 dBuV (108dBuV, PA_BIAS=1) 1010 106.2 dBuV (108.7dBuV, PA_BIAS=1) 1011 106.5 dBuV (109.5dBuV, PA_BIAS=1) 1100 107 dBuV (110.3dBuV, PA_BIAS=1) 1101 107.4 dBuV (111dBuV, PA_BIAS=1) 1110 107.7 dBuV (111.7dBuV, PA_BIAS=1)

108 dBuV (112.5dBuV, PA_BIAS=1) 1111 (default setting)

5.3 Register 0x02 (Address: 0x02, Default: 0x40)

Bit 7 6

KT0806L CHSEL[0] RFGAIN[3] 5

- 4

- 3 2

MUTE PLTADJ Bits Type Default 7 RW 0 6 RW 1 5:4 RW 00 3 RW 0

Label

CHSEL[0]

RFGAIN[3] Reserved MUTE

Description LSB of CHSEL MSB of RFGAIN Reserved Software Mute 0: MUTE Disabled 1: MUTE Enabled

PLTADJ Pilot Tone Amplitude Adjustment

0: Amplitude low 1: Amplitude high

Reserved Reserved PHTCNST Pre-emphasis Time-Constant Set

0: 75 μs (USA, Japan)

1: 50 μs (Europe, Australia)

2 RW 0

1 RW 0 0 RW 0

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