Pin Definitions
Table1-12 lists the pin definitions used in 7series FPGAs packages.
Note:There are dedicated general purpose user I/O pins listed separately in Table1-12. There are
also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#, where ZZZ represents one or more functions in addition to being general purpose user I/O. If not used for their special function, these pins can be user I/O.
IMPORTANT:For Tandem PROM configuration, the configuration PERSIST property is required. In this case, a dual-purpose I/O that is used for stage 1 and stage 2 configuration cannot be repurposed as user I/O after stage 2 configuration is complete.
Table 1-12:7Series FPGAs Pin Definitions
Type
Direction
Description
Most user I/O pins are capable of differential signaling and can be implemented as pairs. The top and bottom I/O pins are always single ended. Each user I/O is labeled IO_LXXY_#, where:
°°
Pin NameUser I/O Pins
IO_LXXY_#IO_XX_#
Dedicated
Input/Output
IO indicates a user I/O pin
L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair# indicates a bank number
°
Configuration Pins
For more information, see the Configuration Pin Definitions table in UG470, 7Series FPGAs Configuration User Guide.CCLK_0DONE_0INIT_B_0
M0_0, M1_0, or M2_0PROGRAM_B_0TCK_0TDI_0TDO_0TMS_0
Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)
Input/OutputBidirectional
Configuration clock. Output in Master mode or input in Slave mode
DONE indicates successful completion of configuration (active High)
Bidirectional Indicates initialization of configuration memory (active (open-drain)Low)
InputInputInputInputOutputInput
Configuration mode selection
Asynchronous reset to configuration logic (active Low)JTAG clockJTAG data inputJTAG data outputJTAG mode select
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
Die Level Bank Numbering Overview
Banking and Clocking Summary
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The center clocking backbone contains all vertical clock tracks and clock bufferconnectivity.
The CMT backbone contains all vertical CMT connectivity and is located in the CMTcolumn.
Not all banks are bonded out in every part/package combination.GTP/GTX/GTH columns summary
°°
One GT Quad=Four transceivers=Four GTPE2 or GTXE2 or GTHE2 primitives.Not all GT Quads are bonded out in every package.
Each bank has four pairs of clock capable (CC) inputs for four differential or foursingle ended clock inputs.----Can connect to the CMT in the same region and the region above and below(with restrictions).
Two MRCC pairs can connect to the BUFRs and BUFIOs in the same region/banksand the regions/banks above and below.
Two SRCC pairs can only connect to the BUFRs and BUFIOs in the same region/bank.
There are no global clock pins (GC pins) in the 7series FPGAs.
?I/O banks summary
°
°
Each user I/O bank has 50 single-ended I/Os or 24 differential pairs (48 differential I/Os). The top and bottom I/O pin are always single ended. All 50 pads of a bank are not always bonded out to pins.
In most devices, banks 14 and 15 always contain the dual-purpose configurationpins. Bank 15 and 35 contains the XADC auxiliary inputs; however, in Kintex-7 devices, the auxiliary inputs are only in bank 15. Bank 0 contains the dedicated configuration pins.
All dedicated configuration I/Os (bank 0) are 3.3V capable.
The multi-function configuration banks 14 and 15 are restricted during
configuration. The SSI technology devices (XC7VX1140T and XC7V2000T) pins in banks 11, 12, 17, 18, 20, and 21 are restricted, similar to multi-function pins. Pins in these banks do not have configuration functions. Because there are architectural differences between these and other banks, special consideration must be taken. For more information, see the State of I/Os During and After Configuration and the
?Bank locations of dedicated and dual-purpose pins
°
°°
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
XC7S6, XA7S6, XC7S15, and XA7S15 Banks
Figure1-1 shows the I/O and transceiver banks.
FTGB196 Package
All HR I/O banks are fully bonded out in this package.
CPGA196 Package
All HR I/O banks are fully bonded out in this package.
CSGA225 Package
All HR I/O banks are fully bonded out in this package.
X-Ref Target - Figure 1-1Left I/OColumn BanksBank 14HRPLL00Right I/OColumnBanksCMTMMCM0016 BUFGsPLL10CMTMMCM10Bank 34HRBank50 I/OsCMTBackboneClockingBackboneCMTBackboneUG475_c1_s1_042717Figure 1-1:XC7S6, XA7S6, XC7S15, and XA7S15 Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
XC7S50 and XA7S50 Banks
Figure1-3 shows the I/O and transceiver banks.
FTGB196 Package
HR I/O banks 15, 16, and 35 are not bonded out.
CSGA324 Package
HR I/O bank 16 is partially bonded out.
FGGA484 Package
All HR I/O banks are fully bonded out in this package.
X-Ref Target - Figure 1-3Left I/OColumn BanksBank 16HRBank 15HRBank 14HRPLL02Right I/OColumnBanksCMTMMCM02PLL01PLL11HROWCMTMMCM01PLL00CMT16 BUFGs16 BUFGsMMCM11PLL10Bank 35HRHorizontal CenterCMTMMCM00CMTMMCM10Bank 34HRBank50 I/OsCMTBackboneClockingBackboneCMTBackboneUG475_c1_S3_042717Figure 1-3:XC7S50 and XA7S50 Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 1:Packaging Overview
XC7A75T and XA7A75T Banks
Figure1-8 shows the I/O and transceiver banks.
FTG256 Package (XC7A75T only)
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HR I/O banks 13 and 16 are not bonded out.HR I/O bank 34 is partially bonded out.
The GTP Quads 213 and 216 are not bonded out.
CSG324 Package
???
HR I/O bank 13 is not bonded out.HR I/O bank 16 is partially bonded out.
The GTP Quads 213 and 216 are not bonded out.
FGG484 Package
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HR I/O bank 13 is partially bonded out.The GTP Quad 213 is not bonded out.
FGG676 Package (XC7A75T only)
All HR I/O banks and the GTP Quads are fully bonded out in this package.
X-Ref Target - Figure 1-8Left I/OColumn BanksBank 16HRBank 15HRBank 14HRBank 13HRPLL03Right I/OColumnBanksCMTMMCM03PLL02PLL11GTP Quad 216Bank 35HRQuadGTPCMTMMCM02 PLL01CMT16 BUFGs16 BUFGsMMCM11PLL10Horizontal CenterCMTMMCM01PLL00CMTMMCM10Bank 34HRBank50 I/OsCMTMMCM00HROWGTP Quad 213CMTBackboneClockingBackboneCMTBackboneUG475_c1_50_011714Figure 1-8:XC7A75T and XA7A75T Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
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