FPGA可编程逻辑器件芯片EP2SGX30CF780C3N中文规格书 - 图文

1.StratixIII Device Data Sheet: DC and

Switching Characteristics

SIII52001-2.1

Electrical Characteristics

Operating Conditions

When Stratix?III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of StratixIII devices, system designers must consider the operating requirements discussed in this chapter. StratixIII devices are offered in both

commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3, –4 and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speedgrades.

1

In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with “C” prefix and industrial with “I” prefix.

Commercial devices are therefore indicated as C2, C3, C4, and C4L per respective speed grades. Industrial devices are indicated as I3, I4, and I4L.

Absolute Maximum Ratings

Absolute maximum ratings define the maximum operating conditions for StratixIII devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional

operation of the device is not implied at these conditions. Conditions beyond those listed in Table1–1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods may have adverse effects on the device.

Table1–1.StratixIII Device Absolute Maximum Ratings (Note1)(Part 1 of 2)

SymbolVCCLVCCVCCD_PLLVCCA_PLLVCCPTVCCPGMVCCPDVCCIOVCC_CLKINVCCBATVI

Parameter

Selectable core voltage power supplyI/O registers power supplyPLL digital power supplyPLL analog power supply

Programmable power technology power supplyConfiguration pins power supplyI/O pre-driver power supplyI/O power supply

Differential clock input power supply (top and bottom I/O banks only)

Battery back-up power supply for design security volatile key registerDC Input voltage

Minimum-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5

Maximum1.651.651.653.753.753.93.93.93.753.754.0

UnitVVVVVVVVVVV

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics

Electrical Characteristics

Table1–3.StratixIII Device Recommended Operating Conditions(Part 2 of 2)Symbol

Parameter

Configuration pins power supply, 3.3 V

VCCPGM

Configuration pins power supply, 3.0 VConfiguration pins power supply, 2.5 VConfiguration pins power supply, 1.8 VI/O pre-driver power supply, 3.3 V

VCCPD (1)

I/O pre-driver power supply, 3.0 VI/O pre-driver power supply, 2.5 VI/O power supply, 3.3 VI/O power supply, 3.0 V

VCCIO

I/O power supply, 2.5 V I/O power supply, 1.8 VI/O power supply, 1.5 V I/O power supply, 1.2 V

VCC_CLKINVCCBAT (3)VIVO

Differential clock input power supply (top and bottom I/O banks only)

Battery back-up power supply for design security volatile key registerDC Input voltageOutput voltage

Conditions

—————————————————For commercial

useFor industrial use(2)Normal POR (PORSEL=0)Fast POR (PORSEL=1)Normal POR (PORSEL=0)Fast POR (PORSEL=1)

Minimum3.1352.852.375 1.71 3.135 2.85 2.3753.1352.85 2.375 1.71 1.4251.14 2.3751.0-0.300-4050 μs50 μs50 μs50 μs

Typical3.332.51.8 3.332.53.332.51.8 1.5 1.2 2.5—————————

Maximum3.4653.152.6251.893.4653.152.6253.4653.152.6251.891.5751.262.625

UnitVVVVVVVVVVVVVVVVV°C°C————

3.33.6VCCIO851005 ms5 ms100 ms12 ms

TJOperating junction temperature

Power Supply Ramptime (For VCCPT)

tRAMP

Power Supply Ramptime (For all power supplies except VCCPT)

Notes to Table1–3:

(1)VCCPD is 2.5 V, 3.0 V, or 3.3 V. For a 3.3-V I/O standard, VCCPD=3.3 V. For a 3.0-V I/O standard, VCCPD = 3.0 V. For a 2.5 V or lower I/O standard,

VCCPD = 2.5 V.(2)For the EP3SL340, EP3SE260, and EP3SL200 devices in the I4L ordering code, the industrial junction temperature range is from 0° C to

100° C, regardless of supply voltage.(3)Altera recommends a 3.0-V nominal battery voltage when connecting VCCBAT to a battery for volatile key backup. If you do not use the volatile

security key, you may connect the VCCBAT to either GND or a 3.0-V power supply.

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsSwitching Characteristics

Final numbers are based on actual silicon characterization and testing. These numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. The upper-right hand corner of a table shows the designation as Preliminary or Final.

Core Performance Specifications

These sections describe the Clock Tree, PLL, DSP, TriMatrix, and Configuration and JTAG Specifications.

Clock Tree Specifications

Table1–19 lists the clock tree performance specifications for the logic array, DSP blocks, and TriMatrix Memory blocks for StratixIII devices.Table1–19.StratixIII Clock Tree Performance

DeviceEP3SL50EP3SL70EP3SL110EP3SL150EP3SL200EP3SE260EP3SL340EP3SE50EP3SE80EP3SE110

C2VCCL = 1.1V600600600600600600600600600600

C3, I3VCCL = 1.1V500500500500500500500500500500

C4, I4VCCL = 1.1V450450450450450450450450450450

C4L, I4L

VCCL = 1.1V450450450450450450450450450450

VCCL = 0.9V375375375375375375375375375375

MHzMHzMHzMHzMHzMHzMHzMHzMHzMHzUnit

PLL Specifications

Table1–20 describes the StratixIII PLL specifications when operating in both the commercial junction temperature range (0 to 85° C) and the industrial junction temperature range (-40 to 100° C), except for EP3SL340, EP3SE260, and EP3SL200 devices in the I4L ordering code, where the industrial junction temperature range is from 0° C to 100° C, regardless of supply voltage. Refer to the figure in “PLL Specifications” in “Glossary” for PLL block diagram.

Stratix III Device Handbook, Volume 2

Stratix III Device Handbook, Volume 2Table1–20.StratixIII PLL Specifications(Part 1 of 3)

C2

C3, I3C4, I4C4L, I4L

Symbol

Parameter

VCCL = 1.1VVCCL = 1.1VVCCL = 1.1VVCCL = 1.1VVCCL = 0.9VUnit

Min

TypMaxMinTypMaxMinTypMaxMinTypMaxMinTypMaxf800 INInput clock frequency 5—(1)5—717 (1)5—717 (1)5—717 (1)5—717 (1)MHzfINPFDInput frequency to the PFD5—3255—3255—3255—3255—325MHzfVCOPLL VCO operating range600—1600600—1300600—1300600—1300600—1300MHztInput clock or external feedback EINDUTYclock input duty cycle

40—6040—6040—6040—6040—60%fOutput frequency for internal global 600 OUTor regional clock

——(2)——500 (2)——450 (2)——450 (2)——375 (2)MHzfOutput frequency for dedicated OUT_EXTexternal clock output

——800 (2)——717 (2)——717 (2)——717 (2)——717 (2)MHztDuty cycle for external clock output OUTDUTY(when set to 50%)455055455055455055455055455055%tExternal feedback clock FCOMPcompensation time

——10——10——10——10——10nstTime required to reconfigure scan CONFIGPLLchain

—3.5——3.5——3.5——3.5——3.5—scanclk cyclestTime required to reconfigure phase CONFIGPHASEshift

—1——1——1——1——1—scanclk cyclesfSCANCLKscanclk frequency

——100——100——100——100——100MHztTime required to lock from end of LOCK

device configuration

—

—

1

—

—

1

—

—

1

—

—

1—

—

1

ms

Time required to lock dynamically t(after switchover or reconfiguring DLOCKany non-post-scale ——1——1——1——1——1ms

counters/delays)

Chapter 1:StratixSwitching CharacteristicsIII Device Data Sheet: DC and Switching CharacteristicsChapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsSwitching Characteristics

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics

I/O Timing

Stratix III Device Handbook, Volume 2