Ball Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4 de-vices. All pins listed may not be supported on the device defined in this data sheet. Seethe Ball Assignments section to review all pins used on this device.
Table 3: Ball Descriptions
SymbolA[17:0]TypeInputDescriptionAddress inputs: Provide the row address for ACTIVATE commands and the columnaddress for READ/WRITE commands to select one location out of the memory array inthe respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have addi-tional functions, see individual entries in this table.) The address inputs also providethe op-code during the MODE REGISTER SET command. A16 is used on some 8Gb and16Gb parts. A17 connection is part-number specific; Contact vendor for more infor-mation.Auto precharge: A10 is sampled during READ and WRITE commands to determinewhether auto precharge should be performed to the accessed bank after a READ orWRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sam-pled during a PRECHARGE command to determine whether the PRECHARGE appliesto one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged,the bank is selected by the bank group and bank addresses.Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine ifburst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chop-ped). See the Command Truth Table.Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along withCS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated asrow address inputs for the ACTIVATE command. When ACT_n is HIGH (along withCS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as nor-mal commands that use the RAS_n, CAS_n, and WE_n signals. See the CommandTruth Table.Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE,READ, WRITE, or PRECHARGE command is being applied. Also determines whichmode register is to be accessed during a MODE REGISTER SET command.Bank group address inputs: Define the bank group to which an ACTIVATE, READ,WRITE, or PRECHARGE command is being applied. Also determines which mode regis-ter is to be accessed during a MODE REGISTER SET command. BG[1:0] are used in thex4 and x8 configurations. BG1 is not used in the x16 configuration.Stack address inputs: These inputs are used only when devices are stacked; that is,they are used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins arenot used in the x16 configuration, and are NC on the x4/x8 SDP). DDR4 will support atraditional DDP package, which uses these three signals for control of the second die(CS1_n, CKE1, ODT1). DDR4 is not expected to support a traditional QDP package. Forall other stack configurations, such as a 4H or 8H, it is assumed to be a single-load(master/slave) type of configuration where C0, C1, and C2 are used as chip ID selectsin conjunction with a single CS_n, CKE, and ODT signal.Clock: Differential clock inputs. All address, command, and control input signals aresampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.A10/APInputA12/BC_nInputACT_nInputBA[1:0]InputBG[1:0]InputC0/CKE1,C1/CS1_n,C2/ODT1InputCK_t,CK_cInput8Gb: x4, x8, x16 DDR4 SDRAM
Ball Descriptions
Table 3: Ball Descriptions (Continued)
SymbolCKETypeInputDescriptionClock enable: CKE HIGH activates and CKE LOW deactivates the internal clock sig-nals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGEPOWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down(row active in any bank). CKE is asynchronous for self refresh exit, however, timingparameters such as tXS are still calculated from the first rising clock edge where CKEHIGH satisfies tIS. After VREFCA has become stable during the power-on and initializa-tion sequence, it must be maintained during all operations (including SELF REFRESH).CKE must be maintained HIGH throughout read and write accesses. Input buffers (ex-cluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Inputbuffers (excluding CKE and RESET_n) are disabled during self refresh.Chip select: All commands are masked when CS_n is registered HIGH. CS_n providesfor external rank selection on systems with multiple ranks. CS_n is considered part ofthe command code.Input data mask: DM_n is an input mask signal for write data. Input data is maskedwhen DM is sampled LOW coincident with that input data during a write access. DMis sampled on both edges of DQS. DM is not supported on x4 configurations. TheUDM_n and LDM_n pins are used in the x16 configuration: UDM_n is associated withDQ[15:8]; LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are en-abled by mode register settings. See the Data Mask section.On-die termination: ODT (registered HIGH) enables termination resistance internalto the DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t,DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations(when the TDQS function is enabled via mode register). For the x16 configuration, RTTis applied to each DQ, UDQS_t, UDQS_c, LDQS_t, LDQS_c, UDM_n, and LDM_n signal.The ODT pin will be ignored if the mode registers are programmed to disable RTT.Parity for command and address: This function can be enabled or disabled via themode register. When enabled, the parity signal covers all command and address in-puts, including ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n,BA[1:0], and BG[1:0] with C0, C1, and C2 on 3DS only devices. Control pins NOT cov-ered by the parity signal are CS_n, CKE, and ODT. Unused address pins that are densi-ty- and configuration-specific should be treated internally as 0s by the DRAM paritylogic. Command and address inputs will have parity check performed when com-mands are latched via the rising edge of CK_t and when CS_n is LOW.Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n andACT_n) define the command and/or address being entered. See the ACT_n descrip-tion in this table.Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inac-tive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_nis a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of VDD (960 mVfor DC HIGH and 240 mV for DC LOW).Connectivity test mode: TEN is active when HIGH and inactive when LOW. TENmust be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DCHIGH and LOW at 80% and 20% of VDD (960mV for DC HIGH and 240mV for DCLOW). On Micron 3DS devices, connectivity test mode is not supported and the TENpin should be considered NF maintained LOW at all times.CS_nInputDM_n,UDM_nLDM_nInputODTInputPARInputRAS_n/A16,CAS_n/A15,WE_n/A14RESET_nInputInputTENInput8Gb: x4, x8, x16 DDR4 SDRAM
Ball Assignments
Figure 6: 96-Ball x16 Ball Assignments
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1.See Ball Descriptions.
2.A slash “/” defines a mode register selectable function, command/address function, den-sity, or package dependence.
3.Address bits (including bank groups) are density- and configuration-dependent (see Ad-dressing).
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