vhdl 试题

B when S=\ C when S=\ D when S=\ E when S=\

F when S=\

G when S=\ H ; end mux;

八选一须具选择器：用CASE语句。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux_8_1 IS

PORT (A,B,C,D,E,F,G,H,En:IN STD_LOGIC; S:in STD_LOGIC_vector(2 downto 0);

Y: out STD_LOGIC); end mux_8_1;

ARCHITECTURE mux OF mux_8_1 begin

process( S,A,B,C,D,E,F,G,H,En) begin

if En='0' then case S is

when \ when \ when \ when \ when \ when \ when \ when \ end case; end if; end process; end mux;

2. 编写实现三-八译码器的VHDL程序；

1。用CASE语句

LIBRARY IEEE;

IS USE IEEE.STD_LOGIC_1164.ALL;

ENTITY LS138 IS

PORT ( S:in STD_LOGIC_vector(2 downto 0);

Y: out STD_LOGIC_vector(7 downto 0));

end LS138;

ARCHITECTURE mux_behave OF LS138 IS begin

PROCESS(S) IS

BEGIN

CASE S IS

when \

when \

when \

when \

when \

when \

when \

when \

END CASE;

END PROCESS;

end mux_behave;

3. 编写实现全加器的VHDL程序，项目名称用fulladder,输入用Ain，Bin ,Cin,

输出用Sum和Co； 全加器：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY full_adder IS

PORT (Ain,Bin ,Cin :IN STD_LOGIC; Sum,Co: out STD_LOGIC ); end full_adder;

ARCHITECTURE rtl OF full_adder BEGIN

Sum<=Ain Xor Bin xor Cin ;

Co<= (Ain and Bin) or ( Ain Xor END rtl;

4. 编写实现半加器的VHDL程序。 半加器1

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY halfadder IS

PORT (A,B:IN STD_LOGIC; Co: out STD_LOGIC; S: out STD_LOGIC);

end halfadder;

ARCHITECTURE rtl OF halfadder BEGIN

S <=A XOR B; Co <=A AND B; END rtl;

IS Bin ) and IS Cin ;