74LS373

SN54LS373, SN54LS374, SN54S373, SN54S374,SN74LS373, SN74LS374, SN74S373, SN74S374OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPSSDLS165B – OCTOBER 1975 – REVISED AUGUST 2002DChoice of Eight Latches or Eight D-TypeDDDDDFlip-Flops in a Single Package3-State Bus-Driving OutputsFull Parallel Access for LoadingBuffered Control InputsClock-Enable Input Has Hysteresis toImprove Noise Rejection (’S373 and ’S374)P-N-P Inputs Reduce DC Loading on DataLines (’S373 and ’S374)SN54LS373, SN54LS374, SN54S373,SN54S374 . . . J OR W PACKAGESN74LS373, SN74S374 . . . DW, N, OR NS PACKAGESN74LS374 . . . DB, DW, N, OR NS PACKAGESN74S373 . . . DW OR N PACKAGE(TOP VIEW)descriptionThese 8-bit registers feature 3-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. Thehigh-impedance 3-state and increasedhigh-logic-level drive provide these registers withthe capability of being connected directly to anddriving the bus lines in a bus-organized systemwithout need for interface or pullup components.These devices are particularly attractive forimplementing buffer registers, I/O ports,bidirectional bus drivers, and working registers.The eight latches of the ’LS373 and ’S373 aretransparent D-type latches, meaning that whilethe enable (C or CLK) input is high, the Q outputsfollow the data (D) inputs. When C or CLK is takenlow, the output is latched at the level of the datathat was set up.The eight flip-flops of the ’LS374 and ’S374 areedge-triggered D-type flip-flops. On the positivetransition of the clock, the Q outputs are set to thelogic states that were set up at the D inputs.OC1Q1D2D2Q3Q3D4D4QGND1234 567891020191817161514131211VCC8Q8D7D7Q6Q6D5D5QC??C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.SN54LS373, SN54LS374, SN54S373,SN54S374 . . . FK PACKAGE(TOP VIEW)1D1QOCVCC8Q2D2Q3Q3D4D45678321201918171615149101112138D7D7Q6Q6D?C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system designas ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A bufferedoutput-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logiclevels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus linessignificantly.OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or newdata can be entered, even while the outputs are off.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright ? 2002, Texas Instruments IncorporatedOn products compliant to MIL-PRF-38535, all parameters are testedunlss othrwis notd. On all othr products, productionprocessing does not necessarily include testing of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265?4QGNDC?5Q5D1SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002SN54LS373, SN54LS374, SN54S373, SN54S374,SN74LS373, SN74LS374, SN74S373, SN74S374OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPSORDERING INFORMATIONTAPACKAGE?TubePDIP– NPDIP NTubeTubeTubeTubeTape and reelTubeto70°C0°CC to 70SOIC– DWDWSOIC Tape and reelTubeTape and reelTubeTape and reelTape and reelSOP – NSSSOP – DBTape and reelTape and reelTape and reelTubeTubeTubeCDIP– JCDIP JTubeTubeTubeTube–55°C to 125°CCFP – WTubeTubeTubeTubeTubeLCCC– FKLCCC FKTubeTubeTubeORDERABLEPART NUMBERSN74LS373NSN74LS374NSN74S373NSN74S374NSN74LS373DWSN74LS373DWRSN74LS374DWSN74LS374DWRSN74S373DWSN74S373DWRSN74S374DWSN74S374DWRSN74LS373NSRSN74LS374NSRSN74S374NSRSN74LS374DBRSN54LS373JSNJ54LS373JSN54LS374JSNJ54LS374JSN54S373JSNJ54S373JSN54S374JSNJ54S374JSNJ54LS373WSNJ54LS374WSNJ54S374WSNJ54LS373FKSNJ54LS374FKSNJ54S373FKSNJ54S374FKTOP-SIDEMARKINGSN74LS373NSN74LS374NSN74S373NSN74S374NLS373LS374S373S37474LS37374LS37474S374LS374ASN54LS373JSNJ54LS373JSN54LS374JSNJ54LS374JSN54S373JSNJ54S373JSN54S374JSNJ54S374JSNJ54LS373WSNJ54LS374WSNJ54S374WSNJ54LS373FKSNJ54LS374FKSNJ54S373FKSNJ54S374FK ?Package drawings, standard packing quantities, thermal data, symbolization, and PCB designguidelines are available at www.ti.com/sc/package.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265? SN54LS373, SN54LS374, SN54S373, SN54S374,SN74LS373, SN74LS374, SN74S373, SN74S374OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPSSDLS165B – OCTOBER 1975 – REVISED AUGUST 2002Function Tables’LS373, ’S373(each latch)INPUTSOCLLLHCHHLXDHLXXOUTPUTQHLQ0Z’LS374, ’S374(each latch)INPUTSOCLLLHCLK↑↑LXDHLXXOUTPUTQHLQ0ZPOST OFFICE BOX 655303 DALLAS, TEXAS 75265?3