8.Contour Drawing &Block Diagram 7.010.513.249.915.018.3870.00.550.240.0(VA)33.24(AA)K4-1.0 PTH2020-1.0 PTH1.8P2.54*19=48.2688.015.0814.065.0A32.4628.02.593.00.580.072.0(VA)66.52(AA)1.513.6 MAX9.014.02.52.54-2.5 PTH4-6.5 PADLED B/L1.61234567891011121314151617181920VssVddVoD/IR/WEDB0DB1DB2DB3DB4DB5DB6DB7CS1CS2RESVoutAK0.520.48The non-specified tolerance of dimension is 0.3mm.0.520.48DOT SIZELED B/L Drive Method1.Drive from A,K KS0107Com1~64Com DriverR128X64 DOTKS0108Seg1~64KS0108Seg65~128AKB/LFR,M,CL,CLK1,CLK22.Drive from pin19, pin20RRBias andPower CircuitSeg DriverD/IR/WEDB0~DB7CS1CS2RESSeg DriverAB/LKMPU80 seriesor68 seriesVddVoVssLCMVR10K~20K(Will never get Vee output from pin19)3.Drive from Vdd,VssRN.V.GeneratorVoutAB/LKLCM(Contrast performance may go down.)External contrast adjustment.
Page 9 of 25 WS-EP-008 10(A)
9.Timing Characteristics MPU Interface (T=25℃, VDD=+5.0V±0.5)
Characteristic E cycle E high level width E low level width E rise time E tall time Address set-up time Address hold time Data set-up time Data delay time Data hold time (write) Data hold time (read) Symbol tcyc twhE twlE tr tf tas tah tdsw tddr tdhw tdhr Min 1000 450 450 － － 140 10 200 － 10 20 Typ － － － － － － － － － － － Max － － － 25 25 － － － 320 － － Unit ns ns ns ns ns ns ns ns ns ns ns tcyc2.0V0.8VtwIEtrtastastwhEtahtah2.0VEtfR/WCS1,CS2,D/IDB0 to DB70.8VtdswtdhwMPU Write Timing
tcyctwIEE2.0V0.8VtwhEtr2.0V0.8Vtftahtah2.0VR/WtastasCS1,CS2,D/IDB0 to DB70.8VtddrtdhrMPU Read Timing
Page 10 of 25 WS-EP-008 10(A)
10.Display Control Instruction The display control instructions control the internal state of the KS0108B. Instruction is received
from MPU to KS0108B for the display control. The following table shows various instructions Instruction D/I R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Controls the display on or Display ON/OFF off. Internal status and 0 0 0 0 1 1 1 1 1 0/1 display RAM data are not affected. 0:OFF, 1:ON Sets the Y address in the Y address counter. Sets the X address at the X address register. Indicates the display data 0 0 1 1 Display start line(0~63) RAM displayed at the top of the screen. Read status. B R 0 ON/OFF E S E T 0 0 0 0 BUSY 0:Ready 1:In operation ON/OFF 0:Display ON 1:Display OFF RESET 0:Normal 1:Reset Writes data (DB0:7)into display data RAM. After 1 0 Display Data writing instruction, Y address is increased by 1 automatically. Set Address Set Page (X address) Display Start Line 0 0 0 0 0 1 1 0 Y address (0~63) 1 1 1 Page (0 ~7) Status Read 0 1 U S Y Write Display Data Read Display Data Reads data (DB0:7) from 1 1 Display Data display data RAM to the data bus. Page 11 of 25 WS-EP-008 10(A)
11.Detailed Explanation Display On/Off
0 0 0 0 1 1 1 1 1 D
The display data appears when D is and disappears when D is 0. Though the data is not on the screen with D = 0, it remains in the display data RAM. Therefore, you can make it appear by changing D = 0 into D = 1.
Display Start Line
R/W D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 A A A A A A
Z address AAAAAA ( binary ) of the display data RAM is set in the display start line register
and displayed at the top of the screen. Figure 2. shows examples of display ( 1/64 duty cycle ) when the start line = 0-3. When the display duty cycle is 1/64 or more ( ex. 1/32, 1/24 etc. ), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed
Set Page ( X Address )
R/W D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 1 A A A
X address AAA ( binary ) of the display data RAM is set in the X address register. After that,
writing or reading to or from MPU is executed in this specified page until the next page is set. See Figure 1.
Set Y Address
R/W D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 A A A A A A
Y address AAAAAA ( binary ) of the display data RAM is set in the Y address counter. After
that, Y address counter is increased by 1 every time the data is written or read to or from MPU.
Status Read
Page 12 of 25 WS-EP-008 10(A)
R/W D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
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