基于Libero的数字逻辑设计仿真及验证实验报告

#10 sel = sel +1; end

endmodule

//74HC85代码

// 74HC85.v

module HC85(DateA, DateB, Cas, Q); input [3:0] DateA, DateB; input [2:0]Cas; output reg [2:0]Q; interger I;

always @(DateA or DateB or Cas) begin if(DateA==DateB) begin if(Cas[1]) Q = 3'b010; else if(Cas==3'b000) Q = 3'b101; else if(Cas==3'b101) Q = 3'b000; else Q = Cas; end else begin for(I=0;I<4;I=I+1) if(DateA[I]>DateB[I]) Q = 3'b100; else if(DateA[I]

endmodule

//74HC85测试平台代码 // test_85.v

`timescale 1ns/1ns module test_85; reg [3:0] a,b; reg [2:0] cas; wire [2:0] res;

HC85 u(a, b, cas, res);

task cascade_input; begin

#0 cas = 0; #10 cas = 1; #10 cas = 3'b100; 12

#10 cas = 3'b101;

#10 cas = 3'b010; #10 cas = 3'b011; #10 cas = 3'b110; #10 cas = 3'b111; #10; end endtask

initial begin a = 4'd9;

b = a; cascade_input(); b = 4'd7; cascade_input(); end

endmodule

//74HC283代码

// 74HC283.v

module HC283(DateA, DateB, Cin, Sum, Cout); input [3:0] DateA, DateB; input Cin;

output [3:0] Sum; output Cout; reg [4:0]Buf;

assign {Cout,Sum} = Buf;

always @(DateA or DateB or Cin) Buf = DateA + DateB + Cin + 5'd0; endmodule

//74HC283测试平台代码 // test_283.v

`timescale 1ns/1ns module test_283; reg [3:0] a, b; reg in;

wire [3:0]sum; wire out; interger I;

HC283 u(a, b, in, sum, out);

task accumulate; begin

a = 4'b0100; for(I=0;I<16;I=I+1)

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begin b = I; #10; end endtask

initial begin

in = 0; accumulate(); in = 1; accumulate(); end

endmodule

//74HC4511代码

// 74HC4511.v

module HC4511(DateOut, DateIn, LE, BL_N, LT_N); output [7:0]DateOut; input [3:0]DateIn; input LE, BL_N, LT_N; reg [7:0]Buf;

assign DateOut = Buf;

always @(DateIn or LE or BL_N or LT_N) begin if(!LT_N) Buf = 8'b11111111; else if(!BL_N) Buf = 8'b0000000; else if(LE) Buf = Buf; else case(DateIn) 4'd0:Buf = 8'b00111111; 4'd1:Buf = 8'b00000110; 4'd2:Buf = 8'b01011011; 4'd3:Buf = 8'b01001111; 4'd4:Buf = 8'b01100110; 4'd5:Buf = 8'b01101101; 4'd6:Buf = 8'b01111101; 4'd7:Buf = 8'b00000111; 4'd8:Buf = 8'b01111111; 4'd9:Buf = 8'b01101111; 4'ha:Buf = 8'b01110111; 4'hb:Buf = 8'b01111100; 4'hc:Buf = 8'b00111001;

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end

4'hd:Buf = 8'b01011110; 4'he:Buf = 8'b01111001; 4'hf:Buf = 8'b01110001; default:; endcase

2、第一次仿真结果（任选一个模块，请注明）

74HC148

3、综合结果

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