基于Libero的数字逻辑设计仿真及验证实验报告

1: Q <= 1; 2: Q <= 0; default: case({J,K}) 0: Q <= Q; 1: Q <= 0; 2: Q <= 1; default: Q <= ~Q; endcase endcase endmodule

//74HC112测试平台代码 // test_112.v

`timescale 1ns/1ns module test_112; reg set, res, clk, j, k; wire q, qn;

HC112 u(set, res, clk, j, k, q, qn);

always

#5 clk = ~clk;

task clock; repeat(3) begin

j = 0;k = 1;#20; j = 1;k = 0;#20; j = 0;k = 0;#20; j = 1;k = 1;#20; end endtask

initial begin

clk = 0;

set = 0;res = 0;clock; set = 0;res = 1;clock; set = 1;res = 0;clock; set = 1;res = 1;clock; end

endmodule

//74HC161代码

20

// 74HC161.v

module HC161(CP,CEP,CET,MRN,PEN,Dn,Qn,TC); input CP;

input CEP,CET; output [3:0]Qn; input MRN,PEN; input [3:0]Dn; output TC; reg [3:0]qaux;

always@(posedge CP, negedge MRN) begin

if(!MRN)

qaux<=4'b0000; else if(!PEN)

qaux<=Dn; else if(CEP & CET) qaux<=qaux+1; else

qaux<=qaux; end

assign TC=(&qaux)&CET;

assign Qn=qaux; endmodule

//74HC161测试平台代码 // 161testbench.v `timescale 1ns/1ns module fre_testbench; reg CP,CEP,CET,MRN; reg LT_N,BI_N,LE; reg [3:0]Dn; wire TC; wire [3:0]Qn; wire [7:0]Seg;

initial begin CP=0;

CEP=1; CET=1; MRN=0; LT_N=1; BI_N=1; LE=0;

21

#10 MRN<=1; end

parameter clock_period=20;

always #(clock_period/2) CP=~CP;

initial begin

Dn=4'b0010;

@(posedge TC)Dn=4'b0100; @(posedge TC)Dn=4'b1000; @(posedge TC)Dn=4'b1010; @(posedge TC)Dn=4'b1110; end

frequency fre_test(CP,CEP,CET,MRN,Dn,Seg,LT_N,BI_N,LE,Qn,TC); endmodule

//74HC194代码 // 74HC194.v

module HC194(DataOut, ParIn, SerIn, Sel, Clk, MR_N); output reg [3:0] DataOut; input [3:0] ParIn; input [1:0] SerIn, Sel; input Clk, MR_N;

always @(negedge MR_N or posedge Clk) if(~MR_N) DataOut <= 0; else

case(Sel)

2'b00: DataOut <= DataOut;

2'b01:If(SerIn[1]) DataOut <= {1'b1,DataOut[3:1]}; else DataOut <= DataOut>>1;

2'b10:if(SerIn[0]) DataOut <= {DataOut[2:0],1'b1}; else DataOut <= DataOut<<1; default: DataOut <= ParIn; endcase endmodule

//74HC194测试平台代码 // test_194.v

`timescale 1ns/1ns module test_194;

22

wire [3:0] out; reg [3:0] p ,t[0:3]; reg [1:0] s, sel; reg mr,clk;

HC194 u(out, p, s, sel, clk, mr);

always #2 clk = ~clk;

task s_clock; begin

s = 0; repeat(4)

#10 s = s+1;

end endtask

task clock; begin

sel = 2'b11; s_clock; sel = 2'b00; s_clock; sel = 2'b01; s_clock; sel = 2'b10; s_clock; end endtask

initial begin

clk = 1; p = 4'b0110; clock; end

initial begin

mr = 1; #5 mr = 0; #10 mr = 1; end

endmodule

2、第一次仿真结果（任选一个模块，请注明）

74HC74

23