FPGA课程设计--基于VHDL的2FSK的信号发生器

when 54=>value<=\ when 55=>value<=\ when 56=>value<=\ when 57=>value<=\ when 58=>value<=\ when 59=>value<=\ when 60=>value<=\ when 61=>value<=\ when 62=>value<=\ when 63=>value<=\ when 64=>value<=\ when 65=>value<=\ when 66=>value<=\ when 67=>value<=\ when 68=>value<=\ when 69=>value<=\ when 70=>value<=\ when 71=>value<=\ when 72=>value<=\ when 73=>value<=\ when 74=>value<=\ when 75=>value<=\ when 76=>value<=\ when 77=>value<=\ when 78=>value<=\ when 79=>value<=\ when 80=>value<=\ when 81=>value<=\ when 82=>value<=\ when 83=>value<=\

when 84=>value<=\ when 85=>value<=\ when 86=>value<=\ when 87=>value<=\ when 88=>value<=\ when 89=>value<=\ when 90=>value<=\ when 91=>value<=\ when 92=>value<=\ when 93=>value<=\ when 94=>value<=\ when 95=>value<=\ when 96=>value<=\ when 97=>value<=\ when 98=>value<=\ when 99=>value<=\ when others=>NULL; END CASE; END PROCESS;

END PSKFSK_ARCH;

5、参考资料

[1] 褚振勇，齐亮．FPGA设计及应用[M] ．西安：西安电子科技大学出版社，2006．