FPGA可编程逻辑器件芯片EP3C10U256C7N中文规格书

2.Intel Agilex I/O Features and UsageUG-20214 | 2021.04.05

ParameterConditionValuesDefault

??

Description

None—specifies a simple wireconnection from/to the buffer.

Simple register—specifies that theDDIO is used as a simple register insingle data-rate mode (SDR). TheFitter may pack this register in theI/O.

DDIO— specifies that the IP usesthe DDIO.

?

Enable synchronousclear / preset port

?

Register mode =DDIO

???

NoneClearPreset

None

Specifies how to implementsynchronous reset port.

?None—Disables synchronous reset

port.

?Clear—Enables the SCLR port for

synchronous clears.

?Preset—Enables the SSET port for

synchronous preset.Specifies how to implementasynchronous reset port.

?None—Disables asynchronous reset

port.

?Clear—Enables the ACLR port for

asynchronous clears.

?Preset—Enables the ASET port for

asynchronous preset.

Enable

asynchronous

clear / preset port

?

Register mode =DDIO

???NoneClearPreset

None

ACLR and ASET signals are active high.

Enable clock enableports

Register mode =DDIO

??

OnOff

Off

?

On—exposes the clock enable(CKE) port to allow you to controlwhen data is clocked in or out. Thissignal prevents data from beingpassed through without yourcontrol.

Off—clock enable port is notexposed and data always pass

through the register automatically.

?

Half Rate logic

Register mode =DDIO

??OnOff

Off

If turned on, enables half-rate DDIO.Refer to Input Path Waveform in DDIOMode with Half-Rate Conversion figurein Input Path section.

If turned on, enables separate clocks(CK_IN and CK_OUT) for the input andoutput paths in bidirectional mode.

Separate input /output Clocks

??

Data Direction =Bidir

Register mode =Simple register orDDIO

??OnOff

Off

Related Information??

Input Path on page 37

Guideline: Swap datain_h and datain_l Ports in Migrated IP on page 35

2.3.2.2.3. IP Core Generation Output (Intel Quartus Prime Pro Edition)

The Intel Quartus Prime software generates the following output file structure forindividual IP cores that are not part of a Platform Designer system.

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2.Intel Agilex I/O Features and Usage

UG-20214 | 2021.04.05

Figure 14.Individual IP Core Generation Output (Intel Quartus Prime Pro Edition)

.ip- Top-level IP variation file - IP core variation files.bsf - Block symbol schematic file .cmp - VHDL component declaration.ppf - XML I/O pin information file.qip - Lists files for IP core synthesis.spd - Simulation startup scripts

_bb.v - Verilog HDL black box EDA synthesis file*_generation.rpt - IP generation report_inst.v or .vhd - Lists file for IP core synthesis.qgsimc- Simulation caching file (Platform Designer).qgsynthc - Synthesis caching file (Platform Designer)sim - IP simulation files.vor vhd - Top-level simulation file - Simulator setup scripts

synth - IP synthesis files.v or .vhd - Top-level IP synthesis file_ - IP Submodule Library

sim - IP submodule 1 simulation files

synth - IP submodule 1 synthesis files

_tb - IP testbench system *

_tb.qsys - testbench system file_tb - IP testbench files

your_testbench>_tb.csv or .spd - testbench file

sim - IP testbench simulation files *If supported and enabled for your IP core variation.Table 12.

Output Files of Intel FPGA IP Generation

File NameDescriptionTop-level IP variation file that contains the parameterization of an IP core inyour project. If the IP variation is part of a Platform Designer system, theparameter editor also generates a .qsys file.The VHDL Component Declaration (.cmp) file is a text file that contains localgeneric and port definitions that you use in VHDL design files.IP or Platform Designer generation log file. Displays a summary of themessages during IP generation.continued... .ip.cmp_generation.rptSend Feedback