FPGA可编程逻辑器件芯片EP3C120F484C7中文规格书

3.Intel Agilex I/O TerminationUG-20214 | 2021.04.05

The OCT calibration process uses the RZQ pin that is available in every calibrationblock in a given I/O bank for series- and parallel-calibrated termination:?????

Each OCT calibration block has an external 240 Ω reference resistor associatedwith it through the RZQ pin.

Connect the RZQ pin to GND through an external 240 Ω resistor.

The RZQ pin shares the same VCCIO_PIO supply voltage with the I/O bank wherethe pin is located.

The RZQ pin is a dual-purpose I/O pin and functions as a general-purpose I/O pinif you do not use the calibration circuit.

Only the 1.2 V VCCIO_PIO bank can use the OCT calibration block.

3.1.3. Single-ended I/O Standards External Termination

SSTL-12, HSTL-12, POD12 I/O standards require an input VREF and a terminationvoltage (VTT). The reference voltage of the receiving device tracks the terminationvoltage of the transmitting device.

Intel recommends that you use OCT with these I/O standards to save board space andcost. OCT reduces the number of external termination resistors used.

Note: Table 30.

You cannot use RS and RT OCT simultaneously. For more information, refer to therelated information.

I/O Standards Required External Termination

I/O Standard

1.2 V LVCMOSSSTL-12HSTL-12HSUL-12POD12

Differential SSTL-12Differential HSTL-12Differential HSUL-12Differential POD12

External Termination Scheme

No on-board termination required

Single-ended SSTL I/O standard terminationSingle-ended HSTL I/O standard terminationNo on-board termination required

Differential POD I/O standard terminationDifferential SSTL I/O standard terminationDifferential HSTL I/O standard terminationNo on-board termination required

Differential POD I/O standard termination

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3.Intel Agilex I/O Termination

UG-20214 | 2021.04.05

Figure 35.SSTL and HSTL I/O Standards External Termination

VCCIO_PIO/2External Terminationin Transmitter PinsRTFPGAOn-BoardVCCIO_PIO2 RReceiverTOCT Terminationin Receiver Pins2 RTTransmitterVCCIO_PIOSeries OCT2 ROn-BoardVREFTGNDVCCIO_PIO2 RTFPGAOCT in Bidirectional PinsGND2 RT2 RGNDTVREFFPGAOn-BoardFPGASeries OCTSend Feedback

3.Intel Agilex I/O TerminationUG-20214 | 2021.04.05

Figure 36.POD12 I/O Standard External Termination

VCCIOExternalTermination in Transmitter PinsFPGAOn-BoardRTReceiverVCCIOOCT Terminationin Receiver PinsTransmitterRTOn-BoardVCCIOParallelOCT, RTVCCIOFPGAOCT inBidirectionalPinsSeriesOCT RS50 ?VREFVREFOn-BoardFPGARelated InformationDynamic OCT on page 51

Series OCT RS3.1.4. Single-ended I/O Termination Implementation Guide

To implement I/O termination in your design, you can use the Intel Quartus Primesoftware to assign the termination for your pins or instantiate an OCT Intel FPGA IP.

3.1.4.1. Configuring OCT Using Assignment Editor

Table 31.

OCT Assignment Names in Intel Quartus Prime Software

Intel Quartus Prime Assignment Names

Output Termination

Values

Series 34 Ohm with CalibrationSeries 40 Ohm with Calibration

RS without calibration

Output Termination

Series 34 Ohm without CalibrationSeries 40 Ohm without Calibration

RT with calibration

Input Termination

Parallel 50 Ohm with CalibrationParallel 60 Ohm with Calibration

OCT FeaturesRS with calibration

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