More often, resets coming into the device are asynchronous. In this case, the resets must be synchronized internally before being sent to the registers. As shown in Figure 7, the synchronization registers are now inside the FPGA.
Figure 7: Schematic for Internally Synchronized Reset
The equivalent Verilog code is shown in Figure 8. Again, note that only the clock edge is in the sensitivity list for a synchronous reset.
Figure 8: Verilog Code for Internally Generated Reset
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The SDC constraints are similar to the external case except that now the input reset cannot be constrained since it is asynchronous, and should be cut with a set_false_path statement as shown in Figure 9 to avoid these being considered unconstrained paths.
Figure 9: SDC Constraints for Internally Synchronized Reset
Another issue with synchronous resets is their behavior with respect to short pulses (less than a period) on the asynchronous input to the synchronizer flip-flops. On the one hand, this could be viewed as a
disadvantage in that there is a requirement on the asynchronous reset that it be at least one period wide in order to guarantee that it will be captured by the first flip-flop. On the other hand, this could be viewed as an advantage in that this circuit increases noise immunity. Spurious pulses on the asynchronous input
would have a lower chance of being captured by the first flip-flop, so they would not trigger a synchronous reset. In some cases, one might want to increase noise immunity further and reject any asynchronous input reset that is less than n periods wide. This would also be useful for debouncing an asynchronous input reset. In order to do this, the following modification (Figure 10) should be made to the internally synchronized reset:
Figure 10: Schematic for Internally Synchronized Reset with Pulse Extender
Many designs have more than one clock signal. In these cases, a separate reset synchronization circuit
should be used for each clock domain in the design. When PLLs are involved, extra caution should be used. When creating synchronizers for the PLL output clocks, these clock domains will not be reset until the PLL has locked and the PLL output clocks are stable. Also worth noting, if the reset to the PLL is used, this reset does not have to be synchronous to the input clock to the PLL. An asynchronous reset can be used for this. Again, using a reset to the PLL will further delay the assertion of a synchronous reset to the PLL
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output clock domains when using internally synchronized resets. As will be demonstrated in a later section of this document, synchronized asynchronous resets solve this problem rather nicely.
Asynchronous Resets
Asynchronous resets have been the most common form of resets used in circuit design for a very long time. It has been very popular to have one asynchronous reset come into the device and then put on a global buffer and connect to the asynchronous reset pin of every (or almost every) register in the device. This approach has its advantages under certain circumstances, but it is not without pitfalls. It is not always the case that every register in a design requires a reset. This approach is not without its costs in terms of
routing resources and use of LAB-wide control signals. It is good practice to only reset those registers that require it.
One of the biggest advantages of asynchronous resets is that they are not inserted in the data path as synchronous resets are. Hence, they do not negatively impact the data arrival times between registers. Another advantage is that they take effect essentially immediately. As soon as the registers get the reset pulse, regardless of the timing relationship relative to the clock, the registers are reset. It is not dependent on a clock as synchronous resets are.
There isn?t any problem with going into reset asynchronously. Problems can arise however when the reset is released, also referred to as “reset removal”. When reset is removed, it must meet the asynchronous μtSU time. This is checked in TimeQuest with a Recovery time check. Also, when reset is removed, it must meet the asynchronous μtH time. This is checked in TimeQuest with a Removal time check. Together, these checks are referred to as Recovery/Removal Analysis.3
Metastability ZoneIncreased Settling TimeAdditional DelayμtSUμtHRecovery Time CheckRemoval Time CheckμtCO0Relative Distance of Reset Deassertion from Clock Edgeclockreset_n
Figure 11: Metastability Curve
When the reset signal is deasserted and does not pass the recovery or removal time check, the edge is said to have fallen in the metastability zone as shown in Figure 11 above. The consequence of this is that the time it takes for the output of the register to settle to the correct state (based on the data input to the 3
For further information on this topic, refer to Tech Note: Understanding Recovery/Removal Analysis in TimeQuest.
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register) is increased. This additional delay can lead to setup time failures to registers downstream, leading to system failure. Obviously, this situation should be avoided at all costs.
One method of avoiding this is to add a couple of follower registers after the register with the asynchronous reset and use the output of these registers in the design. The follower registers act to synchronize the data to the clock in a manner to remove the metastability issues. The closer these registers can be placed to each other in the device, the better to keep the routing delays to a minimum, which decreases data arrival times and increases MTBF. Note that it is important that these follower registers themselves are not reset, but rather will be initialized over a period of several clock cycles by “flushing out” their current or initial state. Figure 12 below shows a schematic example of this circuit.
Figure 12: Schematic of Asynchronous Reset with Follower Registers
In general, for pipelined designs like this without feedback circuits where there is no sequence dependence on initialization, and when the design can wait several cycles after coming out of reset before beginning operation, this type of reset is acceptable.
The equivalent Verilog code is shown in Figure 13 below. Note how this differs from the synchronous reset code. The active edge of the reset is now in the sensitivity list for the procedural block. It is also important that the follower registers are not in the “else” part of the first procedural block as this would infer a clock enable on the follower registers with the inverse of the reset signal tied to the clock enable. The follower registers should be in a separate procedural block as shown using non-blocking assignments.
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