Figure 13: Verilog Code of Asynchronous Reset with Follower Registers
Constraining an asynchronous reset is simple. By definition, asynchronous resets have a non-deterministic relationship to the clock domains of the registers they are resetting. Therefore, static timing analysis of these resets is not possible; they are usually cut with a set_false_path statement (as shown at the bottom of Figure 14). Because the relationship of the reset to the clock at the register is not known, recovery and removal analysis cannot be run in TimeQuest for this path. Attempting to do so will yield no paths
reported. Even without the false path statement cutting this path, no paths would be reported for recovery and removal.
Figure 14: SDC Constraints for Asynchronous Reset
Besides the potential metastability issues with asynchronous resets, another issue is their susceptibility to noise. A noisy asynchronous reset could cause a spurious reset. For this reason, it is important that the asynchronous reset is debounced and filtered. As mentioned previously, synchronous resets are less susceptible to this problem (although not immune) because they are registered by the clock. In the next section on Synchronized Asynchronous Resets, methods are discussed for avoiding this problem altogether.
Perhaps the biggest problem with asynchronous resets is again related to reset removal. Besides the
potential for metastability issues, there is no guarantee that every register connected to the reset will have the same timing relationship to the clock due to register placement and routing within the device. The effect of this is that within a given clock period, some registers would come out of reset while others won?t until the following clock period. This has the potential for disastrous effects with feedback circuits where the next output of a register is dependent on the current output of other registers. A common example of this is with state machines. One-hot state machines are particularly problematic since only one state bit is set at a time. If more than one state bit is high due to some state bits coming out of reset and not others, then the state machine could enter an illegal state.4 With binary encoded state machines, it is possible to create transitions for unused states back to the reset state, this making it a deterministic state machine. This would allow for graceful recovery from an illegal or unused state.
4
Fortunately, one of the Synthesis settings available now is called “Safe State Machines” that will gracefully recover from an illegal state. However, this setting is OFF by default and would have to be turned ON to take effect.
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Despite the potential for recovery from these cases, they should be avoided whenever possible. One method for avoiding them all together is to use a different reset scheme, referred to as Synchronized Asynchronous Resets, which are discussed in detail in the next section.
Synchronized Asynchronous Resets
In order to avoid some of the problems associated with purely synchronous resets and purely asynchronous reset, a third class of reset called Synchronized Asynchronous Resets can be used. These resets combine the advantages of asynchronous resets (no involvement of the data path for speed and taking effect almost instantaneously) with the advantages of synchronous resets (100% synchronous for timing analysis and resistance to noise). These resets are asynchronously asserted and synchronously deasserted to achieve these goals. As discussed previously, going into reset asynchronously is fine, but coming out of reset asynchronously leads to potential problems with metastability and hazards of unwanted situations with synchronous circuits involving feedback.
Some of the methods of implementing these resets are discussed below. The circuit shown in Figure 15 uses synchronizer registers in a similar manner to synchronous resets, but the asynchronous reset is gated with the output of the registers to assert the resulting reset asynchronously. This circuit will assert the reset asynchronously and deassert it asynchronously; however, it has the disadvantage that there will be a gate delay in the resulting reset path.
Figure 15: Schematic of Synchronized Asynchronous Reset with Gated Reset
A better way to implement this is shown in Figure 16. This takes the gate delay out of the path of the resulting reset. The asynchronous reset input is connected directly to the CLRN pin of the synchronizer registers asserting the resulting reset immediately. When the reset is deasserted, a logic ?1? is clocked though the synchronizers to deassert the resulting reset synchronously.
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Figure 16: Schematic of Synchronized Asynchronous Reset without Gate Delay
The equivalent Verilog code is shown below in Figure 17. The first procedural block creates the
synchronized reset rst_n which then becomes the asynchronous reset for the second procedural block. In both of these blocks, the active edge of the reset is used in the sensitivity list.
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Figure 17: Verilog Code for Synchronized Asynchronous Reset
Again, in order to minimize metastability effects between the two synchronization registers and to increase MTBF, these registers should be located as close as possible in the device to minimize routing delay. The Quartus II Fitter will recognize these registers as synchronizers and do this automatically. In this example, they are both placed within the same LAB.
While the input reset signal reset_n still must be cut with a set_false_path command, the reset that comes from the synchronization registers rst_n can now be timed in TimeQuest with Recovery and Removal Analysis. The SDC file to constrain this design is identical to the one shown in Figure 14. Compiling this
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