TDC-GP2与MSP430F413通讯C程序

#define P4SEL_ (0x001F) /* Port 4 Selection */ DEFC( P4SEL , P4SEL_)

/************************************************************ * DIGITAL I/O Port5/6

************************************************************/

#define P5IN_ (0x0030) /* Port 5 Input */ READ_ONLY DEFC( P5IN , P5IN_)

#define P5OUT_ (0x0031) /* Port 5 Output */ DEFC( P5OUT , P5OUT_)

#define P5DIR_ (0x0032) /* Port 5 Direction */ DEFC( P5DIR , P5DIR_)

#define P5SEL_ (0x0033) /* Port 5 Selection */ DEFC( P5SEL , P5SEL_)

#define P6IN_ (0x0034) /* Port 6 Input */ READ_ONLY DEFC( P6IN , P6IN_)

#define P6OUT_ (0x0035) /* Port 6 Output */ DEFC( P6OUT , P6OUT_)

#define P6DIR_ (0x0036) /* Port 6 Direction */ DEFC( P6DIR , P6DIR_)

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#define P6SEL_ (0x0037) /* Port 6 Selection */ DEFC( P6SEL , P6SEL_)

/************************************************************ * BASIC TIMER

************************************************************/

#define BTCTL_ (0x0040) /* Basic Timer Control */ DEFC( BTCTL , BTCTL_) /* The bit names have been prefixed with \#define BTIP0 (0x01) #define BTIP1 (0x02) #define BTIP2 (0x04) #define BTFRFQ0 (0x08) #define BTFRFQ1 (0x10)

#define BTDIV (0x20) /* fCLK2 , ACLK:256 */

/*#define BTRESET (0x40)*/ /* incorrect :BT is reset and BTIFG is reset if this bit is set */

#define BTHOLD (0x40) /* BT1 is held if this bit is set */

#define BTSSEL (0x80) /* fBT , fMCLK

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(main clock) */

#define BTCNT1_ (0x0046) /* Basic Timer Count 1 */ DEFC( BTCNT1 , BTCNT1_)

#define BTCNT2_ (0x0047) /* Basic Timer Count 2 */ DEFC( BTCNT2 , BTCNT2_)

/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */ #define BT_fCLK2_ACLK (0x00) #define BT_fCLK2_ACLK_DIV256 (BTDIV) #define BT_fCLK2_MCLK (BTSSEL)

/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */

#define BT_fCLK2_DIV2 (0x00) /* fINT , fCLK2:2 (default) */

#define BT_fCLK2_DIV4 (BTIP0) /* fINT , fCLK2:4 */

#define BT_fCLK2_DIV8 (BTIP1) /* fINT , fCLK2:8 */

#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT , fCLK2:16 */

#define BT_fCLK2_DIV32 (BTIP2) /* fINT ,

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fCLK2:32 */

#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT , fCLK2:64 */

#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT , fCLK2:128 */

#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) fCLK2:256 */

/* Frequency of LCD coded with Bits 3-4 */

#define BT_fLCD_DIV32 (0x00) fACLK:32 (default) */

#define BT_fLCD_DIV64 (BTFRFQ0) fACLK:64 */

#define BT_fLCD_DIV128 (BTFRFQ1) fACLK:128 */

#define BT_fLCD_DIV256 (BTFRFQ1+BTFRFQ0) fACLK:256 */

/* LCD frequency values with fBT,fACLK */

#define BT_fLCD_1K (0x00) (default) */

#define BT_fLCD_512 (BTFRFQ0) #define BT_fLCD_256 (BTFRFQ1) */

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/* fINT , /* fLCD , /* fLCD , /* fLCD , /* fLCD , /* fACLK:32 /* fACLK:64 */ /* fACLK:128