block and the micro-controller has been modeled using VHDL as a synchronous finite state machine and synthesized with standard CAD tools.
As regards to the asynchronous logic, the micro-controller was first described in CHP [1], a high-level language well suited to model asynchronous circuits. The model was then refined to obtain the final distributed architecture. Model validation was performed by VHDL simulation, thanks to a CHP to VHDL translator [3]. The synthesis of the CHP model into QDI logic was performed by hand and the schematic manually captured in a standard design framework. The micro-controller is thus built of 1) founder standard cells plus some specific cells (Muller gates) and of 2) founder synchronous low-power memories with additional specific interfaces. Gate-level and CHP co-simulation was then performed in VHDL to validate each block after synthesis.
After place & route, the complete system (excluded the analog block) was validated by simulating a VHDL back-an-notated gate level netlist. Finally, a switch level simulation was performed to estimate the core power consumption and thus determine the Smart Card power reception system characteristics. Fig. 7 describes the complete design flow we have set up.
V. E XPERIMENTAL RESULTS
The chip was fabricated at the STMicroelectronics Crolles plant using a 6 metal-layer 0.25-?m
CMOS process. Pads are included in this first prototype in order to test the chip and perform measurements
on both the digital and analog parts. The total chip area is 16 mm2 including these pads. The on-chip-coil is surrounding the chip (Fig. 8). The coil is made of six turns implemented with the upper five metal layers. Its area is 1.5 mm The CISC micro-controller with its memory represents one million transistors. Fig. 4 shows the stabilization of the NRV current with respect to the VDD current variation.
For validating the chip in a system environment, a reader connected to a PC via an RS232 port was designed. The reader includes the RF oscillator, the 10% ASK modulator, the BPSK detector, and provides 1 W under 6-V conditions. The chip was integrated on a prototype card. When inserting the card into the reader magnetic field (11 gauss, with load), a program is downloaded into the micro-controller RAM and data are exchanged between the external PC and the card. The circuit has been successfully validated using several program downloading, like dumping the micro-controller ROM or identifying a pin number.
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Fig. 7. Design flow for asynchronous micro-controller.
Fig. 8. Chip microphotograph.
VI. CONCLUSION
The chip presented in this paper is the first prototype that fully integrates a Contact-less Smart Card (antenna, power reception, RF communication and digital processing). It demonstrates that the design of such System-On-Chip is feasible using the latest industrial technologies. Future investigations will focus on
the benefits of the use of an asynchronous micro-controller with respect to area gain (VDD smoothing capacitor), design complexity reduction and software simplification.
Another very interesting and promising perspective is to investigate the ability of asynchronous circuits to improve Smart Card circuits resistance against well known attacks such as DPA analysis, fault and glitch attacks [11].
REFERENCES
[1] A. J. Martin, ―Synthesis of asynchronous VLSI circuits,‖ Caltech,CS-TR-93–28, 1993.
[2] H. Hulgaard, S. M. Burns, and G. Borriello, ―Testing asynchronous circuits: A survey,‖ Integration: the
VLSI Journal, vol. 19, pp. 111–131,1995.
[3]M. Renaudin, P. Vivet, and F. Robin, ―A design framework for asynchronous/synchronous circuits
based on CHP to HDL translation,‖ in Proc. ASYNC, Barcelona, Spain, Apr. 1999, pp. 135–144.
[4] , ―ASPRO: an 16-bit RISC asynchronous microprocessor with DSP capabilities,‖ in ESSCIRC ,
Duisburg, Germany, Sept. 1999, pp.428–431.
[5] J. Bouvier, Y. Thorigne, S. A. Hassan, M. J. Revillet, and P. Senn, ―A Smart Card CMOS circuit with
magnetic power and communications interface,‖ in Proc. ISSCC, San Francisco, CA, Feb. 1997, pp. 296–297.
[6] A. Abrial, J. Bouvier, M. Renaudin, and P. Vivet, ―A contactless Smart-Card chip based on an
asynchronous 8-bit microcontroller,‖ in Asynchronous Circuits Design (ACiD) Workshop, Grenoble, France,
Jan./Feb. 2000.
[7] J. Kessels, T. Kramer, G. den Besten, and V. Timm, ―Applying asynchronous circuits in Contactless
Smart Cards,‖ in Proc. ASYNC,Tel Aviv, Israel, Apr. 2000, pp. 36–44.
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[8] M. Renaudin, ―Asynchronous circuits and systems: a promising design alternative ,‖Microelectronics
for Telecommunications: Managing High Complexity and Mobility , vol. 54, no. 1-2, pp. 133–149, Dec. 2000.
[9] ―Composant micro-électronique intégrant des moyens de traitement numérique asynchrone et une
interface de couplage électromagnétique sans contact,‖ French Patent 9 908 485.
[10] Identification cards—contactless integrated circuits cards—proximity cards, Standard ISO/IEC FCD
14 443–2.
[11] D. P. Maher, ―Fault induction attacks, tamper resistance, and hostile reverse engineering in
perspective,‖ in Proc. LNCS 1318, Financial Cryptography , 1997.
中文翻译
固态电路 2001年7月 第36卷 第7期
一种新的非接触式智能IC卡，使用片上天线和一个异步微控制器
André Abrial, Jacky Bouvier, Marc Renaudin,
Member, IEEE, Patrice Senn, Member, IEEE, and Pascal Vivet
摘要:本文介绍了新一代非接触式智能卡芯片，它集成了一个片上线圈，连接到一个电源接收系统和发射/接收模块符合ISO 14443标准兼容，异步准延迟敏感（QDI）8位微控制器。这种新的芯片以外的非接触式智能卡的应用领域，演示了该系统的芯片集成功率接收和管理、射频通信和信号处理是可行的。它综合了模拟/数字以及同步/异步逻辑器件，并安装了一个意法半导体公司的0.25微米、CMOS六金属层的半导体。
索引词：异步处理器，片上线圈，异步准延迟敏感电路，智能卡，系统芯片。
一、介绍
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智能卡市场进入了一个新时代,不断增长的应用于各种领域，新国家愿意使用这种技术。 智能卡越来越无处不在,这一趋势是将读卡器整合在所有类型的设备(电脑、掌声电脑、手机等等)。公民管理，电子商务，以及其他可以通过互联网，良好的车辆，使服务提供商能够开发新的服务，使用智能卡的高安全性的关键因素。
在这种背景下,非接触式智能卡扮演一个重要的角色。非接触诱导降低维护成本,提高了易用性、可靠性和终端用户的满意度。他们根据天线的位置减少了几种类型。它可以是上网卡,模块,或直接集成芯片上。后来的技术大大降低了卡的制造成本。此外，由于用户仍然将卡插在读卡器插槽，交易保持接触卡使用时的安全。由于大多数应用程序需要低成本的低功耗系统,这项工作的目标是在单个芯片上集成天线，符合ISO14443标准的射频发射器/接收器，异步微控制器。整个系统集成在硅片上，是一种新的可靠的低成本非接触式智能卡芯片的方式。
设计这个新智能卡芯片的主要关键技术在第二部分给出。智能卡芯片设计的详细刊登在第三节,设计方法在第四节进行了简要评述。在第五部分给出了实验结果。
二、创新
该芯片的创新在于该协会位于同一芯片上的两个[9]的关键技术：一个带有片上线圈的集成接收系统[5]，和一个8位异步微控制器]。这会使我们采取利用异步逻辑性能的方式，减少设计接收系统的集成功率的约束条件，并增加工作领域的数字处理部分。
事实上,异步逻辑对非接触式智能卡片的应用有三个有趣的优点[6]、[7]。而不是被时钟驱动，异步电路是数据驱动导致一个较低的平均功率消耗。而不是实现一个中央控制单元,异步电路实现分布式控制系统,形成较小的电流峰值,进而降低电磁辐射, 由于电活动随时间分布。最后,而不是被‖时钟定时―,异步电路计时自动调节性能。因此,异步电路QDI电压变化是不敏感的,并且在接收功率上运
行最大的速度。
由于QDI 8位微控制器对电力供应的变化是有力的（见第三节），电力接收系统的设计变得更加容易：较低的平均功率交付,以及峰值功率,简化了供应电源的监管。这不仅使设计更简单,也减少了地区(更小的VDD平滑电容)。最后，因为它的低电流峰值QDI的异步单片机不会干扰负载调制，这种调制用于ISO14443标准之间的卡和读者的通信。这使得单片机运行而芯片是将数据传输到读者从而降低软件的复杂性和内存空间需求。
三、智能CARDCHIP设计
图1 芯片结构
这种智能卡由四个主要模块组成（图1）。射频前端从集成天线恢复电力，这形成了一个具有外
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