NAND02GR4B2CN1F中文资料(2)

Table 9.Address Definitions, x16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8dc0c28c83d049649b6658dfmands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11.Copy Back Program x8 Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 12.Copy Back Program x16 Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13.Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14.Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 15.Electronic Signature Byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 16.Electronic Signature Byte/Word 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17.NAND Flash failure modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 18.Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 40

Table 19.Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 20.Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 21.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 22.DC Characteristics, 1.8V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 23.DC Characteristics, 3V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 24.AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25.AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data. . . 57

Table 27.VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data. . 58

Table 28.VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . . . 59

Table 29.Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 30.Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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List of figures NAND01G-B2B, NAND02G-B2C

List of figures

Figure 1.Logic Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2.Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3.TSOP48 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4.VFBGA63 Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6.Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7.Random Data Output During Sequential Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 8.Cache Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10.Random Data Input During Sequential Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 11.Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12.Page Copy Back Program with Random Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 13.Cache Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 14.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 15.Bad Block Management Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16.Garbage Collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 18.Equivalent Testing Circuit for AC Characteristics Measurement . . . . . . . . . . . . . . . . . . . . 43

Figure 8dc0c28c83d049649b6658dfmand Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 20.Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 21.Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 22.Sequential Data Output after Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 23.Read Status Register AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 24.Read Electronic Signature AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 25.Page Read operation AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 26.Page Program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 27.Block Erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 28.Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 29.Program/Erase Enable waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 30.Program/Erase Disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 31.Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 32.Ready/Busy Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 33.Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 56

Figure 34.Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 35.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . . . . 57

Figure 36.VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline. . . . . . . . . . 58

Figure 37.VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . . . . 59

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NAND01G-B2B, NAND02G-B2C Description

1 Description

ST NAND01G-B2B and NAND02G-B2C Flash 2112 Byte/ 1056 Word Page is a family of

non-volatile Flash memories that uses NAND cell technology. The devices range from 1 Gbit

to 2 Gbits and operate with either a 1.8V or 3V voltage supply. The size of a Page is either

2112 Bytes (2048 + 64 spare) or 1056 Words (1024 + 32 spare) depending on whether the

device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or

x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate

to other densities without changing the footprint.

Each block can be programmed and erased over 100,000 cycles. T o extend the lifetime of

NAND Flash devices it is strongly recommended to implement an Error Correction Code

(ECC).

The devices feature a Write Protect pin that allows performing hardware protection against

program and erase operations.

The devices feature an open-drain Ready/Busy output that can be used to identify if the

Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output

allows the Ready/Busy pins from several memories to be connected to a single pull-up

resistor.

A Copy Back Program command is available to optimize the management of defective

blocks. When a Page Program operation fails, the data can be programmed in another page

without having to resend the data to be programmed.

Each device has Cache Program and Cache Read features which improve the program and

read throughputs for large files. During Cache Programming, the device loads the data in a

Cache Register while the previous data is transferred to the Page Buffer and programmed

into the memory array. During Cache Reading, the device loads the data in a Cache

Register while the previous data is transferred to the I/O Buffers to be read.

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