EDA基于VHDL语言的交通灯设计报告 (3)

complete_2hz<=0; flag_2hz<='0'; else

flag_2hz<='1'; end if; end if;

end process;

process(flag_1khz) --此进程是得到1hz信号 begin

if(flag_1khz 'event and flag_1khz='1') then complete_1hz<=complete_1hz+1; if(complete_1hz=1000)then complete_1hz<=0; flag_1hz<='0'; else

flag_1hz<='1'; end if; end if;

end process;

end architecture one;

2、交通灯控制及倒计时模块

--交通灯控制及计时模块 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity state5 is

port(clk1hz,clk2hz:in std_logic;--1hz倒计时时钟信号

one1,ten1,one2,ten2:out integer range 0 to 10;--倒计时数 ra,ga,ya,rb,gb,yb:out std_logic);--主支干道红黄绿灯 end;

architecture two of state5 is

type states is (st0,st1,st2,st3,st4);--定义五个状态

signal r1,g1,y1,r2,g2,y2:std_logic;

signal a,y11,y22:std_logic;------------------------------------------------- begin

--------------------

---------------------

process(clk1hz)-------5 states

variable st:states;

variable eoc:std_logic;--倒计时结束标志位 variable h1,l1,h2,l2:integer range 0 to 10;

begin--------------------------------------------------------------

if clk1hz'event and clk1hz='1' then case st is when st0=>

st:=st1;

h1:=4;l1:=4;

h2:=4;l2:=9;

when st1=>-----主干道绿灯亮45秒

if eoc='0' then

h1:=4;l1:=4; h2:=4;l2:=9; eoc:='1';

g1<='1';r1<='0';y1<='0';g2<='0';r2<='1';y2<='0'; else

if h1=0 and l1=1 then

st:=st2;eoc:='0';h1:=0;l1:=0;h2:=0;l2:=5; elsif l1=0 then

l1:=9;h1:=h1-1;l2:=l2-1; elsif l2=0 then

l2:=9;h2:=h2-1;l1:=l1-1; else l1:=l1-1;l2:=l2-1;

end if;

end if;

when st2=>-----主干道黄灯亮5秒

if eoc='0' then

h1:=0;l1:=4; h2:=0;l2:=4;

eoc:='1';---------------------------------------------- g1<='0';r1<='0';y1<='1';g2<='0';r2<='1';y2<='0';-------------------------------

else

if l1=1 then

st:=st3;eoc:='0';h1:=0;l1:=0;h2:=0;l2:=0; else l1:=l1-1;l2:=l2-1; end if;

end if;

when st3=>-----支干道绿灯亮25秒

if eoc='0' then

h1:=2;l1:=9; h2:=2;l2:=4; eoc:='1';

g1<='0';r1<='1';y1<='0';g2<='1';r2<='0';y2<='0'; else

if h2=0 and l2=1 then

st:=st4;eoc:='0';h2:=0;l2:=0;h1:=0;l1:=5; elsif l2=0 then

l2:=9;h2:=h2-1;l1:=l1-1; elsif l1=0 then

l1:=9;h1:=h1-1;l2:=l2-1; else l2:=l2-1;l1:=l1-1; end if; end if;

when st4=>------支干道黄灯亮5秒

if eoc='0' then

h1:=0;l1:=4; h2:=0;l2:=4; eoc:='1';

g1<='0';r1<='1';y1<='0';g2<='0';r2<='0';y2<='1'; else

if l2=1 then

st:=st1;eoc:='0';h1:=0;l1:=0;h2:=0;l2:=0; else l1:=l1-1;l2:=l2-1; end if;

end if; end case; end if;

ra<=r1;ga<=g1;ya<=y11;rb<=r2;gb<=g2;yb<=y22;-------------------- one1<=l1;ten1<=h1;one2<=l2;ten2<=h2; end process;

process(clk2hz) begin

if clk2hz'event and clk2hz='1' then a<= not a;

if(y1='1')then y11<=a;else y11<='0';end if; if(y2='1')then y22<=a;else y22<='0';end if; end if;

end process; end;

3、数码管译码显示及位选模块

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity display is

port(clk_1khz:in std_logic;--扫描时钟信号

one1,ten1,one2,ten2:in integer range 0 to 10;

scan:out std_logic_vector(3 downto 0);--片选输出信号 seg_7:out std_logic_vector(7 downto 0));--七段译码输出 end entity display;

architecture three of display is

signal data:integer range 0 to 10;

signal seg77:std_logic_vector(7 downto 0); signal cnt:std_logic_vector(1 downto 0); begin

process(data)-------七段译码 begin

case data is

when 0=>seg77<=\when 1=>seg77<=\when 2=>seg77<=\when 3=>seg77<=\when 4=>seg77<=\when 5=>seg77<=\when 6=>seg77<=\when 7=>seg77<=\when 8=>seg77<=\when 9=>seg77<=\when 10=>seg77<=\when others =>null; end case; end process; seg_7<=seg77;

process(clk_1khz,one1,ten1,one2,ten2)----------数码管动态扫描计数 begin

if clk_1khz'event and clk_1khz='1' then --00到11循环计数器 if cnt=\ else cnt<=cnt+1; end if; end if;

end process;

process(cnt,one1,ten1,one2,ten2)----数码管动态扫描显示 begin case cnt is

when \ when \ when \ when \ when others=>null; end case;

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