IEEE 802.3和以太网(7)

e) Ten-bit Interface (TBI). The TBI is provided by the 1000BASE-X PMA sublayer as a physical instantiation of the PMA service interface. The TBI is recommended for 1000BASE-X systems, since it provides a convenient partition between the high-frequency circuitry associated with the PMA sublayer and the logic functions associated with the PCS and MAC sublayers. The TBI is intended for use as a chip-to-chip interface. No mechanical connector is specified for use with the TBI. The TBI is optional. 10比特接口(TBI,Ten-bit Interface )。TBI被1000BASE-X的PMA(Physical Medium Attachment,物理媒体附加)子层提供作为PMA服务接口的物理实例化。TBI被推荐给1000BASE-X系统，因为它提供了PMA子层相关高频电路与PCS、MAC子层相关逻辑功能之间的便利区分。TBI设计用作芯片到芯片的接口。无机械连接器被指定为何TBI一起使用。TBI是可选的。

f) 10 Gigabit Media Independent Interface (XGMII). The XGMII is designed to connect a 10 Gb/s capable MAC to a 10 Gb/s PHY. While conformance with implementation of this interface is not strictly necessary to ensure communication, it is recommended, since it allows maximum flexibility in intermixing PHYs and DTEs at 10 Gb/s speeds.

The XGMII is intended for use as a chip-to-chip interface. No mechanical connector is specified for use with the XGMII. The XGMII is optional. 10吉比特媒体独立接口(XGMII,10 Gigabit Media Independent Interface )。XGMII被设计用于连接10Gbps能力的MAC到10Gbps的PHY。而为了确保通信，与此接口实现相一致性不严格必须，和这种接口的兼容性是建议的，因为它允许以10Gbps速率混杂PHYs和DTEs时最大的灵活性。XGMII设计用作芯片到芯片的接口。无机械连接器被指定为和XGMII一起使用。XGMII是可选的。

g) 10 Gigabit Attachment Unit Interface (XAUI). The XAUI is designed to extend the connection between a 10 Gb/s capable MAC and a 10 Gb/s PHY. While conformance with implementation of this interface is not strictly necessary to ensure communication, it is recommended, since it allows maximum flexibility in intermixing PHYs and DTEs at 10 Gb/s speeds. The XAUI is intended for use as a chip-to-chip interface. No mechanical connector is specified for use with the XAUI. The XAUI is optional.

第5页共11页

2012-2-16 17:59

IEEE 802.3 架构图解,包括10M,100M,1G,10G。

10吉比特连接单元接口（XAUI，10 Gigabit Attachment Unit Interface）。XAUI 被设计用于扩展10 Gbps能力得到MAC和10 Gbps的PHY之间的连接。而为确保通信，与此接口实现相一致性不严格必须，和这种接口的兼容性是建议的，因为它允许以10Gbps速率混杂PHYs和DTEs时最大的灵活性。XAUI设计用作芯片到芯片的接口。无机械连接器被指定为和XAUI一起使用。XAUI是可选的。Under the International Standards Organization’s Open Systems Interconnection (OSI) model, Ethernet isfundamentally a Layer 2 protocol. An Ethernet PHYsical layer device (PHY), which corresponds to Layer 1 ofthe OSI model, connects the media (optical or copper) to the MAC layer, which corresponds to OSI Layer 2.The 802.3ae specification defines two PHY types: the LAN PHY and the WAN PHY. The WAN PHY has anextended feature set added onto the functions of a LAN PHY. Ethernet architecture further divides the PHY(Layer 1) into a Physical Media Dependent (PMD) and a Physical Coding Sublayer (PCS). The two types ofPHYs are solely distinguished by the PCS.802.3ae规范定义了两种PHY类型：LAN PHY和WAN PHY。WAN PHY有一个附加到LAN PHY功能上的扩展特性集。以太网架构进一步划分PHY（1层）为PMD(Physical Media Dependent，物理媒体相关)和PCS（PhysicalCoding Sublayer，物理编码子层）。这两种类型的PHYs被PCS各自区分开。IEEE 802.3ae PHY系列10GbE标准框架包含两个新的物理层规范：LAN PHY和WAN PHY。另外还有三种PCS子层：10GBASE-X、10GBASE-R和10GBASE-W。前两个属于LAN PHY系列，最后一个属于WAN PHY。LAN PHY和WAN PHY的区别在于帧类型和接口速度。串行LAN PHY（10GBASE-R）采用的是以太网帧，数据速率为10.3125Gb/s（MAC的运行速度为10.000Gb/s；加上64B/66B的编码开销，实际的线路速率为10.000*66/64=10.3125Gb/s）。而WAN PHY则可以将64B/66B编码负荷包装到一个通过SONET连接的STS-192c帧中，数据速率为9.953Gb/s。我们为什么需要WAN PHY？SONET/SDH是光传输网络上采用的主要技术，因而传统的光传输基础设施都建立在工作速率为9.953Gb/s的SONET/SDH协议的基础上。但是，线路速率为10.3125Gb/s的LAN PHY与SONET/SDH的速率不匹配，因而不能在基于SONET/SDH的WAN上传输。WAN PHY是IEEE为让10GbE数据速率适应SONET/SDH速度而提供的方法。WAN PHY可以让10GbE兼容ANSI定义的SONET STS-192c格式和数据速率，以及ITU规定的SDH VC-4-64c容器。WAN PHY并不是严格兼容SONET。它更适于被形容为10GbE的一种适应SONET的变体。它的光传输规格和延时、抖动要求仍然与SONET/SDH网络截然不同。

Figure 1 gives a graphical overview of the architectural components of the LAN / WAN PHYBetween the MAC and the PHY is the XGMII, or 10 Gigabit Media Independent Interface. The XGMII providesfull duplex operation at a rate of 10 Gb/s between the MAC and PHY. Each direction is independent andcontains a 32-bit data path, as well as clock and control signals. In total the interface is 74 bits wide.While XGMII provides a 10 Gb/s pipeline, the separate transmission of clock and data coupled with the timingrequirement to latch data on both the rising and falling edges of the clock results in significant challenge inrouting the bus more than the recommended short distance of 7 cm. For this reason, chip-to-chip, board-

搜索“diyifanwen.net”或“第一范文网”即可找到本站免费阅读全部范文。收藏本站方便下次阅读，第一范文网，提供最新教学研究IEEE 802.3和以太网(7)全文阅读和word下载服务。