FPGA可编程逻辑器件芯片XC6VHX380T-2FFG1923I中文规格书

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

Shared PMA PLL

Overview

This section describes the shared PMA PLL of the GTX_DUAL tile (Figure 5-1). Each

GTX_DUAL tile includes one shared PMA PLL used to generate a high-speed serial clock from a high-quality reference clock (CLKIN). The high-speed clock from this block drives the TX and RX PMA blocks for both GTX transceivers in the tile.

The shared PMA PLL generates the high-speed clock (PLL clock) used by both transceivers in the GTX_DUAL tile. After the shared PMA PLL rate is set (PLL clock), the TX and RX output dividers (dividers ending with _OUT) are set to determine the TX and RX line rates for each transceiver.

Figure 5-1:Shared PMA PLL Detail

Notes:

1.The Serial In Parallel Out (SIPO) block in each receiver uses both edges of the high-speed clock. As a result, the effective RX serial clock rate is 2 x PLL Clock/PLL_RXDIVSEL_OUT_n.

2.The Parallel In Serial Out (PISO) block in each transmitter uses both edges of the high-speed clock. As a result, the effective TX serial clock rate is 2 x PLL Clock/PLL_TXDIVSEL_OUT_n.

3.The parallel clock rate is divided to match the internal datapath width. When INTDATAWIDTH = 0 (16-bit internal width), W =8. When INTDATAWIDTH =1 (20-bit internal width), W =10.

4.Refer to Chapter 9, “Loopback,” about the correct setting of these attributes for specific loopback modes.

5.Nominal operating range.

6.The nominal operating range of the shared PMA PLL in a GTX_DUAL tile is 1.5GHz to 3.25GHz. The nominal operation range of the shared PMA PLL in a GTP_DUAL tile is 1.0GHz to 2.0GHz.

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